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FUJITSU SEMICONDUCTOR DATA SHEET
Version 1.3
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90370 Series
MB90372/F372/V370
DESCRIPTION
The MB90370 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing. The instruction set is designed to be optimized for controller applications which inheriting the AT architecture of F2MC-16LX series and allow a wide range of control tasks to be processed efficiently at high speed. A built-in LPC interface, serial IRQ and PS/2 interface simplifies communication with host CPU and PS/2 devices in computer system. Moreover, SMbus compliant I2C, comparator for battery control and A/D converter implements the smart battery control. With these features, the MB90370 series matches itself as keyboard controller with smart battery control. While inheriting the AT architecture of the F 2MC*1 family, the instruction set for the F2MC-16LX CPU core of the MB90370 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. In addition, the MB90370 has an on-chip 32-bit accumulator which enables processing of long-word data. Notes: *1: F2MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED. *2: Purchase of Fujitsu I2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips.
FEATURES
Clock * * * Embedded PLL clock multiplication circuit Operating clock (PLL clock) can selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz to 16 MHz) Minimum instruction execution time of 62.5 ns (at oscillation of 4 MHz, four times the PLL clock, operation at VCC of 3.3 V)
CPU addressing space of 16 Mbytes * Internal 24-bit addressing
Instruction set optimized for controller applications * * Rich data types (bit, byte, word, long word) Rich addressing mode (23 types)
MB90370 Series
* * High code efficiency Enhanced precision calculation realized by the 32-bit accumulator
Instruction set designed for high level language (C) and multi-task operations * * * Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions
Program patch function (2 address pointer) Improved execution speed * 4-byte instruction queue
Powerful interrupt function * * Priority level programmable : 8 levels 32 factors of stronger interrupt function
Automatic data transmission function independent of CPU operation * * Extended intelligent I/O service function (EI2 OS) Maximum 16 channels
Low-power consumption (standby) mode * * * * * Sleep mode (mode in which CPU operating clock is stopped) Timebase timer mode (mode in which operations other than timebase timer and watch timer are stopped) Stop mode (mode in which all oscillations are stopped) CPU intermittent operation mode Watch mode
Package * LQFP-144 (FPT-144P-M12 : 0.4 mm pitch)
Process * CMOS technology
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MB90370 Series
PRODUCT LINEUP
Part number Parameter Classification ROM size RAM size MB90V370 -- -- 15.7K Bytes Number of instruction Minimum execution time Addressing mode Data bit length Maximum memory space I/O port (N-channel) I/O port (CMOS) I/O port (CMOS with pull-up control) Total MB90F372 Flash type ROM 64K Bytes 6K Bytes : 351 : 62.5 ns / 4 MHz (PLL x 4) : 23 : 1, 8, 16 bits : 16 MBytes : 16 : 72 : 32 : 120 MB90372 Mask ROM
CPU function
I/O port
16-bit reload timer 16-bit PPG timer Bit decoder Parity generator PS/2 interface
Reload timer : 4 channels Reload mode, single-shot mode or event count mode selectable PPG timer : 3 channels PWM mode or single-shot mode selectable Bit decoder Parity generator Selectable odd/even parity PS/2 interface 4 selectable sampling clocks LPC bus interface Universal peripheral Interface GA20 output control Data buffer array Serial IRQ request LPC clock monitor / control : 1 channel : 1 channel : 3 channels : 1 channel : 4 channels : for UPI channel 0 only : 48 bytes : 6 channels
LPC interface
Serial IRQ controller
UART
With full-duplex double buffer (variable data length) Clock asynchronized or clock synchronized transmission (with start and stop bits) can be selectively used I2C (SMbus compliant) : 1 channel Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus Selectable packet error check Timeout detection function Multi-address I2C (SMbus compliant) : 1 channel Support I2C bus of PHILIPS and the SMbus proposed by Intel I2C bus Selectable packet error check Timeout detection function 6 addresses support ALERT function Three bus connection routes can be switched by I2C / multi-address I2C
IC
2
Multi-address I2C
Bridge circuit
Part number Parameter
MB90V370
MB90F372
MB90372
Comparator
A comparator that can change the hysteresis width is contained Battery voltage, mounting/dismounting and instantaneous interruption can be detected Parallel and serial charging/discharging
3
MB90370 Series
Part number Parameter External interrupt Key-on wake-up interrupt 8/10-bit A/D converter 8-bit D/A converter LCD controller/driver Low-power consumption Process Package Operating voltage PGA256 MB90V370 6 independent channels Selectable causes 8 independent channels Causes 8/10-bit resolution Conversion time 8-bit resolution MB90F372 MB90372
: Rise/fall edge, fall edge, "L" level or "H" level : "L" level : 12 channels : Less than 6.13 S (16 MHz internal clock) : 2 channels
Up to 9 SEG x 4 COM Selectable LCD output or CMOS I/O port Stop mode / Sleep mode / CPU intermittent operation mode / Watch mode CMOS LQFP-144 (FPT-144P-M12: 0.4 mm pitch) 3.0~3.6 V @ 16 MHz *
*: Varies with conditions such as the operating frequency (see Section " ELECTRICAL CHARACTERISTICS"). Assurance for the MB90V370 is given only for operation with a tool at power supply voltage of 3.0 V to 3.6 V, an operating temperature of 0 to +25 C, and an operating frequency of 1 MHz to 16 MHz.
PACKAGE AND CORRESPONDING PRODUCTS
Package PGA256 FPT-144P-M12 : Available X : Not available Note: For more information about each package, see Section " PACKAGE DIMENSIONS". X MB90V370 MB90F372 X MB90372 X
DIFFERENCES AMONG PRODUCTS
Memory size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V370 does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V370, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only. (This setting can be changed by the development tool configuration.) * In the MB90372/F372, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH are mapped to bank FF only.
4
MB90370 Series
PIN ASSIGNMENT
P37/ADTG P36 P35 P34 P33 P32 P31 P30 P27 P26 P25 P24 P23 P22 P21 X1 X0 Vss Vcc P20 P17 P16 P15 P14 P13 P12 P11 P10 P07/KSI7 P06/KSI6 P05/KSI5 P04/KSI4 P03/KSI3 P02/KSI2 P01/KSI1 P00/KSI0 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3 RST Vcc Vss X0A X1A PA0/ALR1 PA1/ALR2 PA2/ALR3 PA3/ACO PA4/OFB1 PA5/OFB2 PA6/OFB3 CVcc CVRH1 CVRH2 CVRL CVss PB0/DCIN PB1/DCIN2 PB2/VOL1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
LQFP-144 (TOP VIEW) (FPT-144P-M12)
P77/PPG1 P76/UI3 P75/UO3 P74/UCK3 P73/UI2 P72/UO2 P71/UCK2 P70/UI1 P67/UO1 P66/UCK1 P65/INT5 P64/INT4 P63/INT3 P62/INT2 P61/INT1 P60/INT0 PD7/PPG3 Vss Vcc PF7/V3* PF6/V2* PF5/V1* PF4/COM3* PF3/COM2* PF2/COM1* PF1/COM0* PF0/SEG8* PE7/TO4/SEG7 PE6/TIN4/SEG6 PE5/TO3/SEG5 PE4/TIN3/SEG4 PE3/TO2/SEG3 PE2/TIN2/SEG2 PE1/TO1/SEG1 PE0/TIN1/SEG0 P82/ALERT
* Heavy current pins
PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 AVcc AVR AVss PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 PC4/AN4 PC5/AN5 PC6/AN6 PC7/AN7 PD0/AN8 Vcc Vss MD2 MD1 MD0 PD1/AN9 PD2/AN10 PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4 P80/SCL1 P81/SDA1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
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MB90370 Series
PIN DESCRIPTION
Pin no. Pin name LQFP-144 128,129 20,21 17 58, 57, 56 X0,X1 X0A,X1A RST MD0 ~ 2 P00 ~ P07 109 ~ 116 KSI0 ~ KSI7 117 ~ 124 125, 130~136 137 ~ 143 144 ADTG P40 1 PSCK0 P41 2 PSDA0 P42 3 PSCK1 P43 4 PSDA1 P44 5 PSCK2 P45 6 PSDA2 P46 7 CLKRUN P47 8 SERIRQ H G F F F F Port input F F P10 ~ P17 P20 ~ P27 P30 ~ P36 P37 E
External trigger input pin (ADTG) for the A/D converter. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for PS/2 interface channel 0. This function is selected when PS/2 interface channel 0 is enabled. General-purpose N-ch open-drain I/O port. Serial data I/O pin for PS/2 interface channel 0. This function is selected when PS/2 interface channel 0 is enabled. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for PS/2 interface channel 1. This function is selected when PS/2 interface channel 1 is enabled. General-purpose N-ch open-drain I/O port. Serial data I/O pin for PS/2 interface channel 1. This function is selected when PS/2 interface channel 1 is enabled. General-purpose N-ch open-drain I/O port. Serial clock I/O pin for PS/2 interface channel 2. This function is selected when PS/2 interface channel 2 is enabled. General-purpose N-ch open-drain I/O port. Serial data I/O pin for PS/2 interface channel 2. This function is selected when PS/2 interface channel 2 is enabled. General-purpose N-ch open-drain I/O port. LPC clock status / restart request I/O pin for serial IRQ controller. This function is selected when serial IRQ and LPC clock restart request is enabled. General-purpose I/O port. Serial IRQ data I/O pin for serial IRQ controller. This function is selected when serial IRQ is enabled.
I/O circuit A A B C
Pin status during reset Oscillating Main oscillation input pins. Oscillating Sub-clock oscillation input pins. Reset input External reset input pin.
Function
Mode input Input pin for operation mode specification. Connect this pin directly to Vcc or Vss.
General-purpose I/O ports.
D
Can be used as key-on wake-up interrupt input channel 0 ~ 7. Input is enabled when 1 is set in EICR: EN0 ~ 7 in standby mode. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports. General-purpose I/O ports.
E E E
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MB90370 Series
(Continued)
Pin no. Pin name LQFP-144 P50 9 GA20 P51 10 LFRAME P52 11 LRESET P53 12 LCK P54 ~ P57 13 ~ 16 LAD0 ~ LAD3 P60 ~ P65 93 ~ 98 INT0 ~ INT5 P66 99 UCK1 P67 100 UO1 P70 101 UI1 P71 102 UCK2 P72 103 UO2 P73 104 UI2 P74 105 UCK3 P75 106 UO3 I I I I I I I I I H H
Clock input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Address/Data I/O for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O ports. Can be used as DTP/external interrupt request input channel 0 ~ 5. Input is enabled when 1 is set in ENIR: EN0 ~ 5 in standby mode. General-purpose I/O port. Serial clock I/O pin for UART channel 1. This function is enabled when UART channel 1 enables clock output.
I/O circuit
Pin status during reset
General-purpose I/O port.
Function
H
GA20 output for LPC interface. This function is selected when GA20 function is enabled. General-purpose I/O port.
H
LFRAME input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port.
H
Reset input for LPC interface. This function is selected when LPC interface is enabled. General-purpose I/O port.
Port input General-purpose I/O port.
Serial data output pin for UART channel 1. This function is enabled when UART channel 1 enables data output. General-purpose I/O port. Serial data input pin for UART channel 1. While UART channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART channel 2. This function is enabled when UART channel 2 enables clock output. General-purpose I/O port. Serial data output pin for UART channel 2. This function is enabled when UART channel 2 enables data output. General-purpose I/O port. Serial data input pin for UART channel 2. While UART channel 2 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port. Serial clock I/O pin for UART channel 3. This function is enabled when UART channel 3 enables clock output. General-purpose I/O port. Serial data output pin for UART channel 3. This function is enabled when UART channel 3 enables data output.
7
MB90370 Series
(Continued)
Pin no. Pin name LQFP-144 P76 107 UI3 P77 108 PPG1 P80 71 SCL1 P81 72 SDA1 P82 73 ALERT P90 65 SCL2 P91 66 SDA2 P92 67 SCL3 P93 68 SDA3 P94 69 SCL4 P95 70 SDA4 PA0 ~ PA2 22 ~ 24 ALR1 ~ ALR3 PA3 25 ACO PA4 ~ PA6 26 ~ 28 OFB1 ~ OFB3 PB0 ~ PB1 34, 35 DCIN ~ DCIN2 PB2 36 VOL1 K
Battery 1 power instantaneous interruption monitoring input in comparator circuit.
I/O circuit
Pin status during reset
General-purpose I/O port.
Function
I
Serial data input pin for UART channel 3. While UART channel 3 is operating for input, the input of this pin is used as required and must not be used for any other input. General-purpose I/O port.
I
Output pin for PPG channel 1. This function is enabled when PPG channel 1 output is enabled. General-purpose N-ch open-drain I/O port.
T
Serial clock I/O pin for multi-address I2 C. General-purpose N-ch open-drain I/O port.
T
Serial data I/O pin for multi-address I2C. General-purpose N-ch open-drain I/O port.
J
ALERT output pin for multi-address I2C. General-purpose N-ch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port.
T Port input T
Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port. Serial data I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port.
T
Serial data I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port.
T
Serial clock I/O pin for bridge circuit. General-purpose N-ch open-drain I/O port.
T
Serial data I/O pin for bridge circuit. General-purpose I/O ports.
H
Alarm signal output when battery 1 ~ 3 run down in comparator circuit.
General-purpose I/O port.
H
AC power set signal output in comparator circuit. General-purpose I/O ports.
H
Battery 1 ~ 3 discharge control signal output in comparator circuit.
General-purpose I/O ports.
K Comparator input
AC power monitoring input in comparator circuit.
General-purpose I/O ports.
8
MB90370 Series
(Continued)
Pin no. Pin name LQFP-144 PB3 37 VSI1 PB4 38 VOL2 PB5 39 VSI2 PB6 40 VOL3 PB7 41 VSI3 PC0 ~ PC2 45 ~ 47 SW1 ~ SW3 AN0 ~ AN2 PC3 ~ PC7 48 ~ 52 AN3 ~ AN7 A/D input PD0 ~ PD3 53, 59 ~ 61 AN8 ~ AN11 PD4 ~ PD5 62 ~ 63 DA1 ~ DA2 PD6 ~ PD7 64, 92 PPG2 ~ PPG3 PE0 74 SEG0 TIN1 PE1 75 SEG1 TO1 PE2 76 SEG2 TIN2 O O O Port input H N M
General-purpose I/O ports. A/D converter analog input pin 8 ~ 11. This function is enabled when the analog input specification is enabled (ADER2). General-purpose I/O ports. D/A converter analog output 1 ~ 2. This function is selected when D/A converted is enabled. General-purpose I/O port. Output pin for PPG channel 2 ~ 3. This function is selected when PPG channel 2 ~ 3 output is enabled. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 1. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 1. General-purpose I/O port. Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 2.
I/O circuit
Pin status during reset
General-purpose I/O ports.
Function
K
Battery 1 indicator monitoring input in comparator circuit. General-purpose I/O ports.
K
Battery 2 power instantaneous interruption monitoring input in comparator circuit.
K
Comparator General-purpose I/O ports. input
General-purpose I/O ports.
Battery 2 indicator monitoring input in comparator circuit.
K
Battery 3 power instantaneous interruption monitoring input in comparator circuit. General-purpose I/O ports.
K
Battery 3 indicator monitoring input in comparator circuit. General-purpose I/O ports.
L
Comparator input Battery 1 ~ 3 mount / dismount detection input in comparator circuit. or A/D input A/D converter analog input pin 0 ~ 2. This function is enabled when the analog
input specification is enabled (ADER1). General-purpose I/O ports.
M
A/D converter analog input pin 3 ~ 7. This function is enabled when the analog input specification is enabled (ADER1).
9
MB90370 Series
(Continued)
Pin no. Pin name LQFP-144 PE3 77 SEG3 TO2 PE4 78 SEG4 TIN3 PE5 79 SEG5 TO3 PE6 80 SEG6 TIN4 PE7 81 SEG7 TO4 PF0 82 SEG8 PF1 ~ PF4 83 ~ 86 COM0 ~ COM3 PF5 ~ PF7 87 ~ 89 V1 ~ V3 42 43 44 29 30 31 32 33 19,55,91,127 18,54,90,126 AVCC AVR AVSS CVCC CVRH1 CVRH2 CVRL CVSS Vss Vcc R S R R R R R R - - Power input
Vss power input pin for analog circuits. Power (0 V) input pin. Power (3.3 V) input pin.
I/O circuit
Pin status during reset
General-purpose I/O port.
Function
O
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 2. General-purpose I/O port.
O
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 3. General-purpose I/O port.
O
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 3.
Port input General-purpose I/O port. O
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. External clock input pin for reload timer 4. General-purpose I/O port.
O
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. Event output pin for reload timer 4. General-purpose I/O port.
P
Segment output pin for LCD controller/driver. This function is selected when LCD segment output is enabled. General-purpose I/O port.
P
COM output pin for LCD controller/driver. This function is selected when LCD COM output is enabled. General-purpose I/O port. Power input pin for LCD controller/driver. This function is selected when external voltage divider is enabled. Vcc power input pin for analog circuits.
Q
Power input
Power input
Vref+ input pin for the A/D converter. This voltage must not exceed Vcc. Vref- is fixed to AVSS. Vss power input pin for analog circuits. Vcc power input pin for analog circuits.
Power input
Standard power input pin of the comparator.
10
MB90370 Series
I/O CIRCUIT TYPE
Classification
X1/X1A N-ch P-ch Xout P-ch N-ch Standby mode control
Type
Remarks
A
X0/X0A
Main/Sub clock (main/sub clock crystal oscillator) * At an oscillation feedback resistor of approximately 1 M
B
R
* Hysteresis input * Pull-up resistor approximately 50 k
C
* Hysteresis input
R
P-ch
Pull-up control P-ch Pout Nout
D
N-ch
* CMOS output * Hysteresis input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA
Hysteresis input Standby mode control
R
P-ch
Pull-up control P-ch Pout Nout
E
N-ch
* CMOS output * CMOS input * Selectable pull-up resistor approximately 50 k * IOL = 4 mA
CMOS input Standby mode control
N-ch
F
N-ch
Nout
Hysteresis input Standby mode control
* * * *
N-ch open-drain output Hysteresis input IOL = 4 mA 5V tolerant
11
MB90370 Series
Classification
P-ch
Type
Remarks
G
N-ch
Nout
* N-ch open-drain output * CMOS input * IOL = 4 mA
CMOS input Standby mode control
P-ch
Pout Nout
H
N-ch
* CMOS output * CMOS input * IOL = 4 mA
CMOS input Standby mode control
P-ch
Pout Nout
I
N-ch
* CMOS output * Hysteresis input * IOL = 4 mA
Hysteresis input Standby mode control
N-ch
J
N-ch
Nout
CMOS input Standby mode control
* * * *
N-ch open-drain output CMOS input IOL = 4 mA 5V tolerant
P-ch
Pout Nout
N-ch
K
CMOS input Standby mode control Comparator input
* * * *
CMOS output CMOS input Comparator input IOL = 4 mA
12
MB90370 Series
Classification Type Remarks
P-ch
Pout Nout
N-ch
CMOS input
L
Standby mode control Comparator input
* * * * *
CMOS output CMOS input Comparator input A/D analog input IOL = 4 mA
Analog input
P-ch
Pout Nout
M
N-ch
CMOS input Standby mode control Analog input
* * * *
CMOS output CMOS input A/D analog input IOL = 4 mA
P-ch
Pout Nout
N
N-ch
CMOS input Standby mode control Analog output
* * * *
CMOS output CMOS input D/A analog output IOL = 4 mA
P-ch
Pout Nout
O
N-ch
CMOS input Standby mode control Segment output
* * * *
CMOS output CMOS input Segment output IOL = 4 mA
13
MB90370 Series
Classification Type Remarks
P-ch
Pout Nout
P
N-ch
CMOS input Standby mode control Segment output
* * * *
CMOS output CMOS input Segment output IOL = 12 mA
P-ch
Pout Nout
Q
N-ch
CMOS input Standby mode control LCD driving power supply
* * * *
CMOS output CMOS input LCD driving power supply IOL = 12 mA
P-ch
R
N-ch
IN
* Power supply input protection circuit
P-ch
Analog input enable IN
S
N-ch
* A/D converter reference voltage (AVR) input pin with protection circuit
Analog input enable
N-ch
T
N-ch
Nout
CMOS input Standby mode control
* * * *
N-ch open-drain output CMOS input IOL = 4 mA 5V tolerant
14
MB90370 Series
HANDLING DEVICES
Be sure that the maximum rated voltage is not exceeded (latch-up prevention). A latch-up may occur on a CMOS IC if a voltage higher than VCC or lower than VSS is applied to an input or output pin other than medium-to-high voltage pins. A latch-up may also occur if a voltage higher than the rating is applied between VCC and VSS. A latch-up causes a rapid increase in the power supply current, which can result in thermal damage to an element. Take utmost care that the maximum rated voltage is not exceeded. When turning the power on or off to analog circuits, be sure that the analog supply voltages (AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL) and analog input voltage do not exceed the digital supply voltage (VCC). Stabilize the supply voltages Even within the operation guarantee range of the VCC supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. For voltage stabilization guidelines, the VCC ripple fluctuations (P-P value) at commercial frequencies (50 to 60 Hz) should be suppressed to "10%" or less of the reference VCC value. During a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the "transient fluctuation rate" is 0.1 V/ms or less. Power-on To prevent a malfunction in the built-in voltage drop circuit, secure "50 s (between 0.2 V and 1.8 V)" or more for the voltage rise time during power-on. Treatment of unused input pins An unused input pin may cause a malfunction if it is left open. Every unused input pin should be pulled up or down. Treatment of A/D converter, D/A converter and comparator power pin When the A/D converter, D/A converter and comparator is not used, connect the pins as follows: AVCC = CVCC = VCC, AVSS = AVR = CVSS = CVRL = CVRH1 = CVRH2 = VSS. Notes on external clock When an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of sub-clock mode or stop mode. As shown in diagram below, when an external clock is used, connect only the X0 pin and leave the X1 pin open.
X0
MB90370 series Open
X1
15
MB90370 Series
Power supply pins When a device has two or more VCC or VSS pins, the pins that should have equal potential are connected within the device in order to prevent a latch-up or other malfunction. To reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. The current source should be connected to the VCC and VSS pins of the device with minimum impedance. It is recommended that a bypass capacitor of about 0.1 F be connected near the terminals between VCC and VSS. Analog power-on sequence of A/D converter, D/A converter and comparator The power to the A/D converter, D/A converter and comparator (AVCC, CVCC, AVR, CVRH1, CVRH2 and CVRL) and analog inputs (AN0 ~ AN11, VOL1 ~ 3, VSI1 ~ 3, SW1 ~ 3, DCIN and DCIN2) must be turned on after the power to the digital circuits (VCC) is turned on. When turning off the power, turn off the power to the digital circuits (VCC) after turning off the power to the A/D converter, D/A converter, comparator and analog inputs. When the power is turned on or off, AVR should not exceed AVCC. And CVRH1, CVRH2 and CVRL should not exceed CVCC. Also, when a pin that is used for A/D analog input is also used as an input port, the input voltage should not exceed AVCC. And when comparator analog input is also used as an input port, the input voltage should not exceed CVCC. (The power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.)
16
MB90370 Series
BLOCK DIAGRAM
X0, X0A X1, X1A
Clock control circuit Reset circuit (Watchdog timer) Interrupt controller Timebase timer
CPU
F2MC-16LX series core
Other pins Vss x 4, Vcc x 4, MD0-2, AVcc, AVss, CVcc, CVss
Delayed interrupt generator N-ch open-drain I/O port 8,9 I2C bus (Multi-address) I2C bus
P80/SCL1 P81/SDA1 P82/ALERT P90/SCL2 P91/SDA2 P92/SCL3 P93/SDA3 P94/SCL4 P95/SDA4
6
RST
P00/KSI0 to 8 P07/KSI7 P10 to P17 P20 to P27 P30 to P36 P37/ADTG P40/PSCK0 P41/PSDA0 P42/PSCK1 P43/PSDA1 P44/PSCK2 P45/PSDA2 P46/CLKRUN P47/SERIRQ
8 8 8
CMOS I/O port 0,1,2,3*
8
Key-on wake-up interrupt Bridge circuit
N-ch open-drain I/O port 4 (P47 is CMOS I/O port)
6 2
CMOS I/O port A,B Comparator Battery select circuit
7
3CH PS/2 interface Serial IRQ (6 channels) LPC Interface Bus interface
P50/GA20 P51/LFRAME P52/LRESET P53/LCK P54/LAD0 P55/LAD1 P56/LAD2 P57/LAD3
GateA20 control Voltage comparator UPI (Ch0,1,2,3)
8 3
7
PA0/ALR1 to PA2/ALR3 PA3/ACO PA4/OFB1 to PA6/OFB3 PB0/DCIN PB1/DCIN2 PB2/VOL1 PB3/VSI1 PB4/VOL2 PB5/VSI2 PB6/VOL3 PB7/VSI3 CVRH1, CVRH2, CVRL AVR
A/D converter CMOS I/O port 5
P60/INT0 to 6 P65/INT5 P66/UCK1 P67/UO1 P70/UI1 P71/UCK2 P72/UO2 P73/UI2 P74/UCK3 P75/UO3 P76/UI3 P77/PPG1
6
12
(8/10 bit) D/A converter 16-bit PPG (Ch2,3) CMOS I/O port C,D
2
DTP/External interrupt UART (Ch1,2,3) 16-bit PPG (Ch1) CMOS I/O port 6,7
PC0/AN0/SW1 PC1/AN1/SW2 PC2/AN2/SW3 PC3/AN3 to PC7/AN7 PD0/AN8 to PD3/AN11 PD4/DA1 PD5/DA2 PD6/PPG2 PD7/PPG3
CMOS I/O port E,F
RAM ROM
ROM correction ROM mirroring
Note: P00 to P07, P10 to P17, P20 to P27, P30 to P37: With registers that can be used as input pull-up resistors PF0 to PF7: High current pins
16-bit reload timer (Ch1,2,3,4) LCD controller (9SEG x 4COM)
16
PE0/TIN1/SEG0 PE1/TO1/SEG1 PE2/TIN2/SEG2 PE3/TO2/SEG3 PE4/TIN3/SEG4 PE5/TO3/SEG5 PE6/TIN4/SEG6 PE7/TO4/SEG7 PF0/SEG8* PF1/COM0* to PF4/COM3* PF5/V1* to PF7/V3*
17
MB90370 Series
MEMORY MAP
Single-chip mode
(with ROM mirroring function)
FFFFFFH
ROM area
Address #1
FC0000H
010000H
ROM area
(FF bank image) Address #2 004000H 003FC0H Address #3
Peripheral area RAM area
Register
000100H 0000F8H 000000H : Internal access memory
Peripheral area
: Access not allowed Model Address #1 Address #2 Address #3
MB90372 MB90F372 MB90V370
FF0000H FF0000H FF0000H*1
004000H 004000H 004000H*1
001900H 001900H 003FC0H
*1: The MB90V370 does not contain ROM. Assume that the development tool uses these area for its ROM decode areas. Notes:
* * If single-chip mode (without ROM mirroring function) is selected, see Chapter 31, "ROM Mirroring Function Selection Module" of the MB90370 series H/W manual. ROM data in the FF bank can be seen as an image in the higher 00 bank to validate the small model C compiler. Because addresses of the 16 low-order bits in the FF bank are the same, the table in ROM can be referenced without the "far" specification. For example, when 00C000H is accessed, the contents of ROM at FFC000H are actually accessed. The ROM area in the FF bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. Because ROM data from FF4000H to FFFFFFH is seen as an image at 004000H to 00FFFFH, the ROM data table should be stored in the area from FF4000H to FFFFFFH.
18
MB90370 Series
F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
AH
AL USP SSP PS PC DPR PCB DTB USB SSB ADB
8 bits 16 bits 32 bits
Accumulator (A) User Stack Pointer (USP) System Stack Pointer (SSP) Processor Status (PS) Program Counter (PC) Direct Page Register (DPR) Program Bank Register (PCB) Data Bank Register (DTB) User Stack Bank Register (USB) System Stack Bank Register (SSB) Additional Data Bank Register (ADB)
19
MB90370 Series
* General-purpose registers
Dedicated register Accumulator User stack pointer System stack pointer Internal bus Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
General-purpose register
* Processor status (PS)
15 PS Default value 7 - Default value - ILM 000 6 I 0
13 12 RP 00000 5 S 1 4 T X 3 N X 2 Z X
87 CCR -01XXXXX 1 V X 0 C X : CCR
0
B4 B3 B2 B1 B0 Default value 0 0 0 0 0 ILM0 0
: RP
ILM2 Default value 0
ILM1 0
: ILM
- : Not used X : Undefined
20
MB90370 Series
I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH Abbreviation PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC PDRD PDRE PDRF DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 PGDR PGCSR DDRA DDRB DDRC DDRD Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Port C data register Port D data register Port E data register Port F data register Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Parity generator data register Parity generator control status register Port A direction register Port B direction register Port C direction register Port D direction register Byte access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Word access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Parity generator R/W R/W R/W R/W R/W Port A Port B Port C Port D X------0B -0000000B 00000000B 00000000B 00000000B Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB X1111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB -----111B --111111B -XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 0-------B 00000000B 00000000B 00000000B XXXXXXXXB
21
MB90370 Series
(Continued)
Address 00001EH 00001FH 000020H 000021H 000022H 000023H 000024H 000025H 000026H 000027H 000028H ELVR 000029H 00002AH 00002BH 00002CH 00002DH 00002EH 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH ADER1 ADER2 BRSR ADC0 ADCR0 A/D data register ADCR1 ADCS0 A/D control status register ADCS1 SICRL SICRH SIFR1 SIFR2 SIFR3 SIFR4 PDCRL1 PPG1 down counter register PDCRH1 PCSRL1 PPG1 period setting register PCSRH1 PDUTL1 PPG1 duty setting register PDUTH1 PCNTL1 PPG1 control status register PCNTH1 R/W R/W 00000000B R/W W R/W XXXXXXXXB --000000B W W 16-bit PPG timer (CH1) XXXXXXXXB XXXXXXXXB R W 11111111B XXXXXXXXB Serial interrupt request register Serial interrupt control register Serial interrupt frame number register 1 Serial interrupt frame number register 2 Serial interrupt frame number register 3 Serial interrupt frame number register 4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Serial IRQ 00000000B 00000000B 00000000B --000000B --000000B --000000B --000000B 11111111B R/W R/W R/W R/W Analog input enable register 1 Analog input enable register 2 Bridge circuit selection register A/D control register Request level setting register R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R 8/10-bit A/D converter Port C, A/D Port D, A/D Bridge circuit ----0000B 11111111B ----1111B --000000B 00000000B XXXXXXXXB 00000-XXB 00--------B Abbreviation DDRE DDRF SMR1 SCR1 SIDR1/ SODR1 SSR1 M2CR1 CDCR1 ENIR EIRR Register Port E direction register Port F direction register Serial mode register 1 Serial control register 1 Input data register 1 / Output data register 1 Serial status register 1 Mode 2 control register 1 Clock division control register 1 Interrupt / DTP enable register Interrupt / DTP cause register Byte access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Word access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DTP/external interrupt Communication prescaler 1 UART1 Resource name Port E Port F Initial value 00000000B 00000000B 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B --000000B --XXXXXXB 00000000B
22
MB90370 Series
(Continued)
Address 000040H 000041H 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH Abbreviation PDCRL2 PPG2 down counter register PDCRH2 PCSRL2 PPG2 period setting register PCSRH2 PDUTL2 PPG2 duty setting register PDUTH2 PCNTL2 PPG2 control status register PCNTH2 PDCRL3 PPG3 down counter register PDCRH3 PCSRL3 PPG3 period setting register PCSRH3 PDUTL3 PPG3 duty setting register PDUTH3 PCNTL3 PPG3 control status register PCNTH3 PSCR0 PSSR0 PSCR1 PSSR1 PSCR2 PSSR2 PSDR0 PSDR1 PSDR2 PSMR DAT0 DAT1 DACR0 DACR1 PS/2 interface control register 0 PS/2 interface status register 0 PS/2 interface control register 1 PS/2 interface status register 1 PS/2 interface control register 2 PS/2 interface status register 2 PS/2 interface data register 0 PS/2 interface data register 1 PS/2 interface data register 2 PS/2 interface mode register D/A converter data register 0 D/A converter data register 1 D/A control register 0 D/A control register 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D/A converter R/W R/W -------0B -------0B 3-channel PS/2 interface 00000000B 0--00000B 00000000B 0--00000B 00000000B 0--00000B 00000000B 00000000B 00000000B 00000000B ----0000B XXXXXXXXB XXXXXXXXB R/W W R/W XXXXXXXXB --000000B W W 16-bit PPG timer (CH3) XXXXXXXXB XXXXXXXXB R W 11111111B XXXXXXXXB R/W R/W R 00000000B 11111111B R/W W R/W XXXXXXXXB --000000B W W 16-bit PPG timer (CH2) XXXXXXXXB XXXXXXXXB R W 11111111B XXXXXXXXB Register Byte access Word access R Resource name Initial value 11111111B
23
MB90370 Series
(Continued)
Address 00005EH 00005FH 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H Abbreviation UPAL1 UPAH1 UPAL2 UPAH2 UPAL3 UPAH3 UPCL UPCH UPDI0/ UPDO0 UPS0 UPDI1/ UPDO1 UPS1 UPDI2/ UPDO2 UPS2 UPDI3/ UPDO3 UPS3 LCR ROMM TMCSRL1 TMCSRH1 TMR1/ TMRD1 TMCSRL2 TMCSRH2 TMR2/ TMRD2 Register UPI1 address register (lower) UPI1 address register (upper) UPI2 address register (lower) UPI2 address register (upper) UPI3 address register (lower) UPI3 address register (upper) UPI control register (lower) UPI control register (upper) UPI0 data input register / data output register UPI0 status register UPI1 data input register / data output register UPI1 status register UPI2 data input register / data output register UPI2 status register UPI3 data input register / data output register UPI3 status register LPC control register ROM mirroring function selection register Timer control status register CH1 (lower) Timer control status register CH1 (upper) 16-bit timer/reload register CH1 Timer control status register CH2 (lower) Timer control status register CH2 (upper) 16-bit timer/reload register CH2 R/W XXXXXXXXB R/W R/W R/W R/W R/W R/W 16-bit reload timer (CH2) XXXXXXXXB 00000000B ----0000B XXXXXXXXB Byte access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W Word access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W 16-bit reload timer (CH1) ROM mirroring function LPC interface Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B -000-000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B XXXXXXXXB 00000000B -----000B -------1B 00000000B ----0000B XXXXXXXXB
24
MB90370 Series
(Continued)
Address Abbreviation Register Timer control status register CH3 (lower) Timer control status register CH3 (upper) 16-bit timer/reload register CH3 TMCSRL4 TMCSRH4 Timer control status register CH4 (lower) Timer control status register CH4 (upper) 16-bit timer/reload register CH4 IBCRL IBCRH IBSRL IBSRH IDAR IADR ICCR ITCR ITOC ITOD ISTO IMTO RDR0 RDR1 RDR2 RDR3 I C bus control register (lower) I C bus control register (upper) I2C bus status register (lower) I2C bus status register (upper) I C data register I C address register I C clock control register I2C timeout control register I2C timeout clock register I2C timeout data register I C slave timeout register I C master timeout register Port 0 pull-up resistor setting register Port 1 pull-up resistor setting register Port 2 pull-up resistor setting register Port 3 pull-up resistor setting register
2 2 2 2 2 2 2
Byte access R/W R/W -
Word access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W
Resource name
Initial value
000078H 000079H 00007AH
TMCSRL3 TMCSRH3
00000000B 16-bit reload timer (CH3) ----0000B XXXXXXXXB XXXXXXXXB 00000000B 16-bit reload timer (CH4) ----0000B XXXXXXXXB XXXXXXXXB ----0000B 00000000B 00000000B --000000B XXXXXXXXB -XXXXXXXB I2C 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B Port 0 Port 1 Port 2 Port 3 00000000B 00000000B 00000000B 00000000B
TMR3/TMRD3 00007BH 00007CH 00007DH 00007EH TMR4/TMRD4 00007FH 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH 000090H ~ 9DH 00009EH 00009FH PACSR DIRR
R/W R/W -
R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Prohibited area
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Program address detect control status register Delayed interrupt cause / clear register
R/W R/W
R/W R/W
Address match detection Delayed interrupt
00000000B -------0B
25
MB90370 Series
(Continued)
Address Abbreviation Register Low-power consumption mode register Clock selection register Byte access R/W R/W Prohibited area CKMC Clock modulation control register R/W R/W Clock modulation -------0B Word access R/W R/W Resource name Low-power consumption control register Initial value
0000A0H 0000A1H 0000A2H ~ A3H 0000A4H 0000A5H ~ A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH
LPMCR CKSCR
00011000B 11111100B
Prohibited area WDTC TBTC WTC Watchdog control register Timebase timer control register Watch timer control register R/W R/W R/W Prohibited area EICR EIFR FMCS Wake-up interrupt control register Wake-up interrupt flag register Flash memory control status register R/W R/W R/W Prohibited area ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B 00000111B R/W R/W R/W Wake-up interrupt Flash memory interface circuit 00000000B -------0B 00010000B R/W R/W R/W Watchdog timer Timebase timer Watch timer X-XXX111B 1--00100B 10001000B
26
MB90370 Series
(Continued)
Address 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H Abbreviation MBCRL MBCRH MBSRL MBSRH MDAR MALR MADR1 MADR2 MADR3 MADR4 MADR5 MADR6 MCCR MTCR MTOC MTOD MSTO MMTO SMR2 SCR2 SIDR2/ SODR2 SSR2 M2CR2 CDCR2 Register MI2C bus control register (lower) MI C bus control register (upper) MI C bus status register (lower) MI C bus status register (upper) MI C data register MI2C alert register MI2C address register 1 MI C address register 2 MI C address register 3 MI C address register 4 MI2C address register 5 MI2C address register 6 MI2C clock control register MI C timeout control register MI C timeout clock register MI C timeout data register MI2C slave timeout register MI2C master timeout register Serial mode register 2 Serial control register 2 Input data register 2 / output data register 2 Status register 2 Mode 2 control register 2 Clock division control register 2
2 2 2 2 2 2 2 2 2 2
Byte access R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Word access R/W R/W R R/W R/W R/W R/W R/W R/W
Resource name
Initial value ----0000B 00000000B 00000000B --000000B XXXXXXXXB ----0000B -XXXXXXXB -XXXXXXXB -XXXXXXXB
MI2C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Communication prescaler 2 UART2 -XXXXXXXB -XXXXXXXB -XXXXXXXB 0-000000B -0-00000B 00000000B 00000000B 00000000B 00000000B 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B
27
MB90370 Series
(Continued)
Address Abbreviation Register Comparator control register (lower) Comparator control register (upper) Comparator status register 1 (lower) Comparator status register 1 (upper) Comparator interrupt control register (lower) Comparator interrupt control register (upper) Comparator status register 2 (lower) Comparator status register 2 (upper) Comparator input enable register Bit data register Bit result register (lower) Bit result register (upper) Serial mode register 3 Serial control register 3 Input data register 3 / output data register 3 Status register 3 Mode 2 control register 3 Clock division control register 3 Port 3 data latch register Byte access R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Prohibited area LCRL LCRH VRAM LCD control register 0 LCD control register 1 LCD display RAM R/W R/W R/W Prohibited area External area R/W R/W LCD controller / driver 00010000B 00000000B XXXXXXXXB Word access R/W R/W R/W R/W R/W R/W R R R/W R/W R R R/W R/W R/W R/W R/W R/W R/W Communication prescaler 3 Port 3 data latch UART3 Bit decoder Voltage comparator Resource name Initial value
0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH ~ EDH 0000EEH 0000EFH 0000F0H ~ F4H 0000F5H ~ F7H 0000F8H ~ FFH
COCRL COCRH COSRL1 COSRH1 CICRL CICRH COSRL2 COSRH2 CIER BDR BRRL BRRH SMR3 SCR3 SIDR3 / SODR3 SSR3 M2CR3 CDCR3 PDL3
--000000B 00011111B 00000000B --000000B 00000000B --000000B XXXXXXXXB --XXXXXXB ---11111B ----XXXXB XXXXXXXXB XXXXXXXXB 00000-00B 00000100B XXXXXXXXB 00001000B ----1000B 00--0000B 00000000B
28
MB90370 Series
(Continued)
Address Abbreviation Register Program address detection register 0 PADR0 Program address detection register 1 Program address detection register 2 Program address detection register 3 PADR1 Program address detection register 4 Program address detection register 5 Byte access R/W R/W R/W R/W R/W R/W Word access R/W R/W R/W Address match detection R/W R/W R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB Resource name Initial value
001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H
XXXXXXXXB XXXXXXXXB XXXXXXXXB
29
MB90370 Series
(Continued)
Address 003FC0H 003FC1H 003FC2H 003FC3H 003FC4H 003FC5H 003FC6H 003FC7H 003FC8H 003FC9H 003FCAH 003FCBH 003FCCH 003FCDH 003FCEH 003FCFH 003FD0H 003FD1H 003FD2H 003FD3H 003FD4H 003FD5H 003FD6H 003FD7H 003FD8H 003FD9H 003FDAH 003FDBH 003FDCH 003FDDH 003FDEH 003FDFH 003FE0H 003FE1H 003FE2H 003FE3H Abbreviation UDRL0 UDRH0 UDRL1 UDRH1 UDRL2 UDRH2 UDRL3 UDRH3 UDRL4 UDRH4 UDRL5 UDRH5 UDRL6 UDRH6 UDRL7 UDRH7 UDRL8 UDRH8 UDRL9 UDRH9 UDRLA UDRHA UDRLB UDRHB UDRLC UDRHC UDRLD UDRHD UDRLE UDRHE UDRLF UDRHF DNDL0 DNDH0 DNDL1 DNDH1 Register UP data register 0 (lower) UP data register 0 (upper) UP data register 1 (lower) UP data register 1 (upper) UP data register 2 (lower) UP data register 2 (upper) UP data register 3 (lower) UP data register 3 (upper) UP data register 4 (lower) UP data register 4 (upper) UP data register 5 (lower) UP data register 5 (upper) UP data register 6 (lower) UP data register 6 (upper) UP data register 7 (lower) UP data register 7 (upper) UP data register 8 (lower) UP data register 8 (upper) UP data register 9 (lower) UP data register 9 (upper) UP data register A (lower) UP data register A (upper) UP data register B (lower) UP data register B (upper) UP data register C (lower) UP data register C (upper) UP data register D (lower) UP data register D (upper) UP data register E (lower) UP data register E (upper) UP data register F (lower) UP data register F (upper) DOWN data register 0 (lower) DOWN data register 0 (upper) DOWN data register 1 (lower) DOWN data register 1 (upper) Byte access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R Word access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R LPC data buffer array Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
30
MB90370 Series
(Continued)
Address 003FE4H 003FE5H 003FE6H 003FE7H 003FE8H 003FE9H 003FEAH 003FEBH 003FECH 003FEDH 003FEEH 003FEFH 003FF0H 003FF1H 003FF2H ~ 003FFFH Abbreviation DNDL2 DNDH2 DNDL3 DNDH3 DNDL4 DNDH4 DNDL5 DNDH5 DNDL6 DNDH6 DNDL7 DNDH7 DBAAL DBAAH Register DOWN data register 2 (lower) DOWN data register 2 (upper) DOWN data register 3 (lower) DOWN data register 3 (upper) DOWN data register 4 (lower) DOWN data register 4 (upper) DOWN data register 5 (lower) DOWN data register 5 (upper) DOWN data register 6 (lower) DOWN data register 6 (upper) DOWN data register 7 (lower) DOWN data register 7 (upper) Data buffer array address register (lower) Data buffer array address register (upper) Byte access R R R R R R R R R R R R R/W R/W Prohibited area Word access R R R R R R R R R R R R R/W R/W LPC data buffer array Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Meaning of abbreviations used for reading and writing R/W: Read and write enabled R: W: Read-only Write-only
Explanation of initial values 0: The bit is initialized to 0. 1: The bit is initialized to 1. X: The initial value of the bit is undefined. -: The bit is not used. Its initial value is undefined.
Instruction using IO addressing e.g. MOV A, io, is not supported for registers area 003FC0H to 003FFFH.
31
MB90370 Series
INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt cause
Reset INT9 instruction Exception processing A/D converter conversion termination Timebase timer UPI0 IBF / LPC reset UPI1 IBF UPI2 IBF UPI3 IBF DTP/ext. interrupt channels 0/1 detection DTP/ext. interrupt channels 2/3 detection DTP/ext. interrupt channels 4/5 detection Wake-up interrupt detection UPI0/1/2/3 OBE 16-bit PPG timer 1 PS/2 interface 0/1 PS/2 interface 2 Watch timer I2C transfer complete / bus error 16-bit PPG timer 2/3 Voltage comparator 1 MI2C transfer complete / bus error Voltage comparator 2 I2C timeout / standby wake-up 16-bit reload timer 1/2 underflow MI2C timeout / standby wake-up 16-bit reload timer 3/4 underflow UART1 receive UART1 send UART2 receive UART2 send UART3 receive UART3 send Flash memory status Delayed interrupt generator module O O O O O O O
EI2OS support
X X X O #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42
Interrupt vector Number
08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH
Interrupt control register ICR
ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15
Priority *2
High
Address
FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
Address
0000B0H*1 0000B1H*1 0000B2H*1 0000B3H*1 0000B4H*1 0000B5H*2 0000B6H*1 0000B7H*1 0000B8H*1 0000B9H*1 0000BAH*1 0000BBH*1 0000BCH*1 0000BDH*1 0000BEH*1 0000BFH*1
Low
O: Can be used and interrupt request flag is cleared by EI2OS interrupt clear signal. X: Cannot be used. : Can be used and support the EI2OS stop request. : Can be used.
32
MB90370 Series
*1: For peripheral functions that share the ICR register, the interrupt level will be the same. If the extended intelligent I/O service is to be used with a peripheral function that shares the ICR register with another peripheral function, the service can be started by either of the function. And if EI2OS clear is supported, both interrupt request flags for the two interrupt causes are cleared by EI2OS interrupt clear signal. It is recommended to mask either of the interrupt request during the use of EI2OS. EI2OS service cannot be started multiple times simultaneously. Interrupt other than the operating interrupt is masked during EI2OS operation. It is recommended to mask either of the interrupt requests during the use of EI2 OS.
-
*2: This priority is applied when interrupts of the same level occur simultaneously.
33
MB90370 Series
PERIPHERAL RESOURCES
1. Low-power Consumption Control Circuit
The MB90370 series has the following CPU operating mode selected by the configuration of an operating clock and clock operation control. Clock Mode * PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. * Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions. In the main clock mode, the PLL multiplier circuit is inactive. * Sub-clock mode In this mode, the sub-clock, with the sub-clock (SCLK) frequency divided by 4 is used to operate the CPU and peripheral functions. In the sub-clock mode, the main clock and PLL multiplier circuit are inactive. Reference For the clock mode, see Section 4.4 "Clock Mode" of the MB90370 series H/W manual. CPU Intermittent Operating Mode In this mode, the CPU is operated intermittently while high-speed clock pluses are supplied to peripheral functions, thereby reducing power consumption. In this mode, intermittent clock pulses are supplied only to the CPU while it is accessing a register, internal memory, peripheral function, or external unit. Standby Mode In this mode, the low-power consumption control circuit stops supplying the clock to the CPU (sleep mode) or the CPU and peripheral functions (timebase timer mode) or stops the oscillation clock itself (stop mode), thereby reducing power consumption. * PLL sleep mode The PLL sleep mode is activated to stop the CPU operating clock in the PLL clock mode. Components excluding the CPU operate on the PLL clock. * Main sleep mode The main sleep mode is activated to stop the CPU operating clock in the main clock mode. Components excluding the CPU operate on the main clock. * Sub-sleep mode The sub-sleep mode is activated to stop the CPU operating clock in the sub-clock mode. Components excluding the CPU operate on the divided-by-four sub-clock. * Timebase timer mode The timebase timer mode causes the operation of functions, excluding the oscillation clock, timebase timer, and watch timer, to stop. All functions other than the timebase timer and watch timer are inactivated. 34
MB90370 Series
* Watch mode and main watch mode The watch mode and main watch mode operates the watch timer only. The sub-clock operates but the main clock and PLL multiplier circuit stop. * Stop mode The stop mode causes the oscillation to stop. All functions are inactivated. Note Because the stop mode turns the oscillation clock off, data can be retained by the lowest power consumption.
(1) Register configuration
Clock Selection Register Address: 0000A1H Read/write Initial value
15 SCM R 1
14 MCM R 1
13 WS1 R/W 1
12 WS0 R/W 1
11 SCS R/W 1
10 MCS R/W 1
9 CS1 R/W 0
8 CS0 R/W 0
Bit number CKSCR
Lower Power Consumption Mode Control Register 7 6 5 Address: 0000A0H Read/write Initial value STP W 0 SLP W 0 SPL R/W 0
4 RST W 1
3 TMD W 1
2 CG1 R/W 0
1 CG0 R/W 0
0
Reserved
Bit number LPMCR
R/W 0
35
MB90370 Series
(2) Block diagram
Low power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0
RESV
Pin highimpedance control circuit RSTX Pin CPU intermittent operation selector
Pin Hi-Z control
Internal reset Internal reset generation circuit Intermittent cycle selection CPU clock control circuit CPU clock pulse
2 Interrupt clearing
Standby control circuit
Stop and sleep signals
Stop signal Machine clock Clock generation part Clock selector
Divideby-4 Sub-clock Oscillation stabilization wait clearing
Peripheral clock control circuit
Peripheral clock
2 2 PLL multiplier circuit
System clock generation circuit
Oscillation stabilization wait time selector
Sub-clock generation circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR)
X0A X1A
Pin Pin
X0 X1
Pin
Divideby-2 Main clock
Divideby-8
Divideby-16
Divideby-128
Divideby-4
Divideby-8
Timebase timer
Pin
36
MB90370 Series
2. I/O Ports
(1) Outline of I/O ports Each I/O port outputs data from the CPU to the I/O pins or inputs signals from the I/O pins to the CPU as directed by the port data register (PDR). Each CMOS I/O port can also designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data direction register (DDR). Or N-channel open-drain port can designate the direction of a data flow (input or output) at the I/O pins in bit units using the port data register (PDR). The function of each port and the resources using it are described below: * * * * * * * * * * * * * * * * Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port D Port E Port F : : : : : : : : : : : : : : : : General-purpose I/O port/resource (Key-on wake-up interrupt) General-purpose I/O port General-purpose I/O port General-purpose I/O port/resource (A/D converter external trigger) General-purpose I/O port/resource (PS/2 interface / serial IRQ controller) General-purpose I/O port/resource (LPC interface) General-purpose I/O port/resource (DTP / UART1) General-purpose I/O port/resource (UART1 / UART2 / UART3 / PPG1) General-purpose I/O port/resource (Multi-address I2C) General-purpose I/O port/resource (I2C / Multi-address I2C) General-purpose I/O port/resource (Comparator) General-purpose I/O port/resource (Comparator) General-purpose I/O port/resource (Comparator / A/D converter) General-purpose I/O port/resource (A/D converter / D/A converter / PPG2 / PPG3) General-purpose I/O port/resource (Reload timer1 ~ 4 / LCD controller) General-purpose I/O port/resource (LCD controller)
(2) Register configuration
Register
Port 0 data register (PDR0) Port 1 data register (PDR1) Port 2 data register (PDR2) Port 3 data register (PDR3) Port 4 data register (PDR4) Port 5 data register (PDR5) Port 6 data register (PDR6) Port 7 data register (PDR7) Port 8 data register (PDR8) Port 9 data register (PDR9) Port A data register (PDRA) Port B data register (PDRB) Port C data register (PDRC) Port D data register (PDRD) Port E data register (PDRE) Port F data register (PDRF) Port 0 data direction register (DDR0)
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address
000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH 00000EH 00000FH 000010H
Initial value
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB X1111111B XXXXXXXXB XXXXXXXXB XXXXXXXXB -----111B --111111B -XXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B
37
MB90370 Series
Register
Port 1 data direction register (DDR1) Port 2 data direction register (DDR2) Port 3 data direction register (DDR3) Port 4 data direction register (DDR4) Port 5 data direction register (DDR5) Port 6 data direction register (DDR6) Port 7 data direction register (DDR7) Port A data direction register (DDRA) Port B data direction register (DDRB) Port C data direction register (DDRC) Port D data direction register (DDRD) Port E data direction register (DDRE) Port F data direction register (DDRF) Analog data input enable register (ADER1) Analog data input enable register (ADER2) Comparator input enable register (CIER) LCD control register 1 (LCRH) Port 0 pull-up resistor setting register (RDR0) Port 1 pull-up resistor setting register (RDR1) Port 2 pull-up resistor setting register (RDR2) Port 3 pull-up resistor setting register (RDR3) Port 3 data latch register (PDL3)
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address
000011H 000012H 000013H 000014H 000015H 000016H 000017H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 00002AH 00002BH 0000E0H 0000EFH 00008CH 00008DH 00008EH 00008FH 0000EAH
Initial value
00000000B 00000000B 00000000B 0-------B 00000000B 00000000B 00000000B -0000000B 00000000B 00000000B 00000000B 00000000B 00000000B 11111111B ----1111B ---11111B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B
R/W : Read/write enabled R X - : Read-only : Undefined : Not used
38
MB90370 Series
(3) Block diagram of I/O ports * Block diagram of port 0 pins
RDR Resource input Port data register (PDR)
Pull-up resistor About 50K
PDR read
Output latch
* Block diagram of port 1 pins
Internal data bus
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
RDR Port data register (PDR)
Pull-up resistor About 50K
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
39
MB90370 Series
* Block diagram of port 2 pins
RDR Port data register (PDR)
Pull-up resistor About 50K
PDR read
Output latch
* Block diagram of port 3 pins
Internal data bus Internal data bus 40
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
RDR Port data register (PDR) Resource input
Pull-up resistor About 50K
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read Port data latch register (PDL)
Input latch
R
Standby control (SPL = 1)
MB90370 Series
* Block diagram of port 47 pin
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
* Block diagram of port 46 pin
Internal data bus Internal data bus
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
PDR write Pin Read-Modify-Write instruction
Standby control (SPL = 1)
41
MB90370 Series
* Block diagram of port 45 ~ 40 pins
Resource output Port data register (PDR)
Resource input Resource output enable
* Block diagram of port 5 pins
Internal data bus Internal data bus
PDR read
Output latch
PDR write Pin Read-Modify-Write instruction
Standby control (SPL = 1)
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
42
MB90370 Series
* Block diagram of port 6 pins
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
* Block diagram of port 7 pins
Internal data bus Internal data bus
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
43
MB90370 Series
* Block diagram of port 8 pins
Resource output Port data register (PDR)
Resource input Resource output enable
* Block diagram of port 9 pins
Internal data bus Internal data bus
PDR read
Output latch
PDR write Pin Read-Modify-Write instruction
Standby control (SPL = 1)
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
PDR write Pin Read-Modify-Write instruction
Standby control (SPL = 1)
44
MB90370 Series
* Block diagram of port A pins
Resource output Resource output enable Port data register (PDR)
PDR read
Output latch
* Block diagram of port B pins
Internal data bus Internal data bus
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
CIER Port data register (PDR)
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write Standby control (SPL = 1) DDR read
Comparator operation enable
Comparator input
45
MB90370 Series
* Block diagram of port C7 ~ C3 pins
ADER Port data register (PDR)
* Block diagram of port C2 ~ C0 pins
Internal data bus Internal data bus
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write Standby control (SPL = 1) DDR read
A/D converter channel selection bit
to A/D converter analog input
CIER ADER Port data register (PDR)
Comparator
Comparator operation enable bit (COCRH)
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write Standby control (SPL = 1) DDR read
A/D converter channel selection bit
to A/D converter analog input
46
MB90370 Series
* Block diagram of port D7 ~ D6 pins
Resource output Resource output enable Port data register (PDR)
PDR read
Output latch
* Block diagram of port D5 ~ D4 pins
Internal data bus
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1)
Port data register (PDR)
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read Analog output D/A output enable
Standby control (SPL = 1)
47
MB90370 Series
* Block diagram of port D3 ~ D0 pins
ADER Port data register (PDR) A/D input
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write
DDR read
Standby control (SPL = 1)
* Block diagram of port E pins
Resource output Port data register (PDR)
Resource input Resource output enable
PDR read
Output latch
PDR write Pin Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1) LCD output LCD output enable
48
MB90370 Series
* Block diagram of port F7 ~ F5 pins
LCRH VS LCD input (V1~3) Port data register (PDR)
PDR read
Output latch
PDR write Port data direction register (DDR)
Direction latch
Pin
DDR write
DDR read
Standby control (SPL = 1)
* Block diagram of port F4 ~ F0 pins
Port data register (PDR)
PDR read
Output latch
PDR write
Pin
Port data direction register (DDR)
Direction latch
DDR write
DDR read
Standby control (SPL = 1) LCD output LCD output enable
49
MB90370 Series
3. Timebase timer
The timebase timer is an 18-bit free-running counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation). Features of timebase timer : * Interrupt generated when counter overflow * EI2OS supported * Interval timer function : An interrupt generated at four different time intervals * Clock supply function : Four different clock can be selected as watchdog timer's count clock Supply clock for oscillation stabilization (1) Register configuration
Timebase Timer Control Register 15 Address: 0000A9H Read/write Initial value
Reserved
14
13
12 TBIE R/W 0
11 TBOF R/W 0
10 TBR W 1
9 TBC1 R/W 0
8 TBC0 R/W 0
Bit number TBTC
R/W 1
(2) Block diagram of timebase timer
To watchdog timer Timebase timer counter Divide-by -two HCLK 21 22 23 ... 27 ... 28 29 210 211 212 213 214 215 216 217 218
OF
OF
OF
OF
To the oscillation stabilization wait time selector in the clock control section
Power-on reset Stop mode start CKSCR: MCS = 1 0 (*1) SCS = 1 0 (*2) Timebase timer interrupt signal #12 (0CH)
Counter clear circuit
Interval timer selector TBOF set
: Unused RESV -- -- TBIE TBOF TBR TBC1 TBC0 OF:Overflow Timebase timer interrupt register (TBTC) HCLK: Oscillation clock *1 Switching of the machine clock from the oscillation clock to the PLL clock *2 Switching from main clock to sub-clock
50
MB90370 Series
4. Watchdog timer
The watchdog timer is a 2-bit counter that uses the timebase timer's supply clock as the count clock. After activation, if the watchdog timer is not cleared within a given period, the CPU will be reset. * Features of watchdog timer : Reset CPU at four different time intervals Status bits to indicate the reset causes (1) Register configuration of watchdog timer
Watchdog Timer Control Register 7 Address: 0000A8H Read/write Initial value PONR R X 6 5 WRST R X 4 ERST R X 3 SRST R X 2 WTE W 1 1 WT1 W 1 0 WT0 W 1 Bit number WDTC
(2) Block diagram of watchdog timer
Watchdog timer control register (WDTC) PONR WRST ERST SRST WTE 2 Activation with CLR
Start of watch mode Start of sleep mode Start of stop mode reset generation
WT1
WT0
WDCS (from watch timer control register, WTC)
Watchdog timer Counter clear control circuit
CLR Watchdog reset generator
To the internal reset generator
Count
clock selector CLK
2-bit counter
Overflow
4 4 (Timebase timer counter) One-half of HCLK X2
1
X22
...
X28 X29 X210 X211 X212 X213 X214 X215 X216 X217 X218
Sub-clock divide by 4
X21 X22
.........
X210 X211 X212 X2 13 X214 X215
Watch timer counter
HCLK: Oscillation clock
51
MB90370 Series
5. Watch timer
The watch timer is a 15-bit timer that uses sub-clocks and can generate an interval interrupt. It can also be used as the watchdog timer clock source and sub-clock oscillation wait time. Features of the watch timer : * Provides the watchdog timer clock source * Sub-clock oscillation stabilization wait timer function * Interval timer function that generates interrupts in a given cycle (1) Register configuration of watch timer
Watch Timer Control Register 7 Address: 0000AAH Read/write Initial value WDCS R/W 1 6 SCE R 0 5 WTIE R/W 0 4 WTOF R/W 0 3 WTR W 1 2 WTC2 R/W 0 1 0 Bit number WTC
WTC1 WTC0 R/W 0 R/W 0
(2) Block diagram of watch timer
Watch timer control register (WTC) WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Clear
28 29 210 211 212 213 214 215 Interval selector
The subclock divided by 4
Watch counter
Interrupt generator
Watch timer interrupt
210
213
214
215
To the watchdog timer
52
MB90370 Series
6. 16-bit PPG timer (x 3)
The 16-bit PPG (Programmable Pulse Generator) timer consists of a 16-bit down counter, prescaler, 16-bit period setting register, 16-bit duty setting register, 16-bit control register and a PPG output pin. Features of 16-bit PPG timer : * 8 types of counter operation clock ( , /2, /4, /8, /16, /32, /64, /128) can be selected ( is the machine clock) * An interrupt is generated when there is a trigger or an counter borrow or when PPG rising (normal polarity) / PPG falling (inverted polarity) * PPG output operation The 16-bit PPG timer can output pulse waveforms with variable period and duty ratio. Also, it can be used as D/A converter in conjunction with an external circuit. (1) Register configuration of PPG timer
PPG Down Counter Register (Upper) Address: ch1 000039H ch2 000041H ch3 000049H Read/write Initial value
15
14
13
12
11
10
9
8
Bit number PDCRH1 ~ 3
DC15 DC14 DC13 DC12 DC11 DC10 DC09 DC08
R 1 R 1 7 R 1 6 R 1 5 R 1 4 R 1 3 R 1 2 R 1 1 0
PPG Down Counter Register (Lower) Address: ch1 000038H ch2 000040H ch3 000048H Read/write Initial value
Bit number PDCRL1 ~ 3
DC07 DC06 DC05 DC04 DC03 DC02 DC01 DC00
R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1
PPG Period Setting Buffer Register (Upper) 15 14 13 12 11 10 9 8 Address: ch1 00003BH ch2 000043H ch3 00004BH CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08 Read/write Initial value W X W X 7 W X 6 W X 5 W X 4 W X 3 W X 2 W X 1 0
Bit number PCSRH1 ~ 3
PPG Period Setting Buffer Register (Lower) Address: ch1 00003AH ch2 000042H ch3 00004AH Read/write Initial value
Bit number PCSRL1 ~ 3
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W X W X W X W X W X W X W X W X
53
MB90370 Series
(Continued)
PPG Duty Setting Buffer Register (Upper) 15 14 13 12 11 10 9 8 Address: ch1 00003DH ch2 000045H ch3 00004DH DU15 DU14 DU13 DU12 DU11 DU10 DU09 DU08 Read/write Initial value W X W X W X W X W X W X W X W X
Bit number PDUTH1 ~ 3
PPG Duty Setting Buffer Register (Lower) Address: ch1 00003CH ch2 000044H ch3 00004CH Read/write Initial value
7
6
5
4
3
2
1
0
Bit number PDUTL1 ~ 3
DU07 DU06 DU05 DU04 DU03 DU02 DU01 DU00
W X W X W X W X W X W X W X W X
PPG Control Status Register (Upper) 15 Address: ch1 00003FH ch2 000047H ch3 00004FH Read/write Initial value 14 13 12 11 10 9 8 Bit number PCNTH1 ~ 3 CNTE STGR MDSE RTRG CKS2 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 CKS1 CKS0 PGMS R/W 0 R/W 0 R/W 0
PPG Control Status Register (Lower) 7 Address: ch1 00003EH ch2 000046H ch3 00004EH Read/write Initial value 6 IREN R/W 0 5 IRQF R/W 0 4 IRS1 R/W 0 3 IRS0 R/W 0 2 1 0 Bit number PCNTL1 ~ 3
POEN OSEL R/W 0 R/W 0
Note : Registers PDCR1 ~ 3, PCSR1 ~ 3 and PDUT1 ~ 3 are word access only
54
MB90370 Series
(2) Block diagram of PPG timer
Period setting buffer register 1/2/3
Duty setting buffer register 1/2/3
Prescaler
CKS2 CKS1 CKS0
Period setting register 1/2/3
Duty setting register 1/2/3
1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128
Comparator CLK LOAD
P77/PPG1 or PD6/PPG2 or PD7/PPG3 Pin
16-bit down counter
MDSE PGMS OSEL POEN
STOP START BORROW
Machine clock S
Down counter register 1/2/3
Q
R
Interrupt selection
Interrupt
#22 (for PPG1) or #27 (for PPG2/3)
Gate input
IRS1
IRS0
IRQF
IREN
STGR CNTE RTRG
55
MB90370 Series
7. 16-bit reload timer (x 4)
The 16-bit reload timer provides two operating mode, internal clock mode and event count mode. In each operating mode, the 16-bit down counter can be reloaded (reload mode) or stopped when underflow (one-shot mode). Output pins TO1 ~ TO4 are able to output different waveform according to the counter operating mode. TO1 ~ TO4 toggles when counter underflow if counter is operated as reload mode. TO1 ~ TO4 output specified level ("H" or "L") when counter is counting if the counter is in one-shot mode. Features of the 16-bit reload timer : * Interrupt generated when timer underflow * EI2OS supported * Internal clock operating mode : Three internal count clocks can be selected Counter can be activated by software or external trigger (signal at TIN1 ~ TIN4 pin) Counter can be reloaded or stopped when underflow after activated * Event count operating mode : Counter counts down by one when specified edge at TIN1 ~ TIN4 pin Counter can be reloaded or stopped when underflow (1) Register configuration of reload timer
Timer Control Status Register (Upper) Address: ch1 000071H ch2 000075H ch3 000079H ch4 00007DH Read/write Initial value 15 14 13 12 11 CSL1 R/W 0 10 9 8 MOD1 R/W 0 Bit number
CSL0 MOD2 R/W 0 R/W 0
TMCSRH1 ~ 4
Timer Control Status Register (Lower) Address: ch1 000070H ch2 000074H ch3 000078H ch4 00007CH Read/write Initial value 7 MOD0 R/W 0 6 5 4 RELD R/W 0 3 INTE R/W 0 2 UF R/W 0 1 CNTE R/W 0 0 TRG R/W 0 Bit number
OUTE OUTL R/W 0 R/W 0
TMCSRL1 ~ 4
16-bit Timer Register / 16-bit Reload Register (Upper) Address: ch1 000073H ch2 000077H ch3 00007BH ch4 00007FH Read/write Initial value 15 D15 R/W X 14 D14 R/W X 13 D13 R/W X 12 D12 R/W X 11 D11 R/W X 10 D10 R/W X 9 D09 R/W X 8 D08 R/W X Bit number
TMR1 ~ 4 / TMRD1 ~ 4
16-bit Timer Register / 16-bit Reload Register (Lower) Address: ch1 000072H ch2 000076H ch3 00007AH ch4 00007EH Read/write Initial value 7 D07 R/W X 6 D06 R/W X 5 D05 R/W X 4 D04 R/W X 3 D03 R/W X 2 D02 R/W X 1 D01 R/W X 0 D00 R/W X Bit number
TMR1 ~ 4 / TMRD1 ~ 4
56
MB90370 Series
(2) Block diagram of reload timer
F2MC-16LX Bus
TMRD0*1 TMRD1*1
16-bit reload register
TMR1*1 16-bit timer register Count clock generation circuit Machine clock Prescaler Clear
PE0/TIN1/SEG0 PE2/TIN2/SEG2 PE4/TIN3/SEG4 PE6/TIN4/SEG6
Reload signal
Reload control circuit
Gate input
Valid clock judgment circuit
Wait signal To UART1*1 Output control circuit
Output signal generation circuit
Internal clock Input control circuit Clock selector External clock Select signal Function selection
Pin
P15
Invert
Pin
PE1/TO1/SEG1 PE3/TO2/SEG3 PE5/TO3/SEG5 PE7/TO4/SEG7
Operation control circuit
Timer control status register TMCSR1*1
Interrupt request signal #32 (20H)*1*2 <#34 (22H)>
*1 This register includes channel 1,2,3 and 4. The register enclosed in < and > indicates the
channel 2,3 and 4 register.
*2 Interrupt number, channel 1 and 2 share one interrupt number, channel 3 and 4 share another
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MB90370 Series
8. I2C
The I2 C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (SDA) and a serial clock line (SCL). Among the devices connected with these two wires, information is transmitted to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. Among these devices, the master/slave relation is established. The I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. The communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages. This I2C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic Packet Error Code (PEC) generation and verification. (1) Register configuration of I2C
I2C Bus Control Register (Lower) 7 Address: 000080H Read/write Initial value 6 5 4 3 RES R/W 0 2 PECE R/W 0 1 LBT R/W 0 0 WUE R/W 0 Bit number
IBCRL
I2C Bus Control Register (Upper) 15 Address: 000081H Read/write Initial value BER R/W 0 14 BEIE R/W 0 13 SCC R/W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0 Bit number
IBCRH
I2C Bus Status Register (Lower) 7 Address: 000082H Read/write Initial value BB R 0 6 RSC R 0 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 FBT R 0 Bit number
IBSRL
I2C Bus Status Register (Upper) 15 Address: 000083H Read/write Initial value I2C Data Register 7 Address: 000084H Read/write Initial value D7 R/W X 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Bit number 14 13
PMATCH
12 WUF R/W 0
11 TDR R/W 0
10 TCR R/W 0
9 MTR R/W 0
8 STR R/W 0
Bit number
IBSRH
R 0
IDAR
(Continued)
58
MB90370 Series
(Continued)
I2C Address Register 15 Address: 000085H Read/write Initial value I2C Clock Control Register 7 Address: 000086H Read/write Initial value DMBP R/W 0 6 5 EN R/W 0 4 CS4 R/W 0 3 CS3 R/W 0 2 CS2 R/W 0 1 CS1 R/W 0 0 CS0 R/W 0 Bit number 14 A6 R/W X 13 A5 R/W X 12 A4 R/W X 11 A3 R/W X 10 A2 R/W X 9 A1 R/W X 8 A0 R/W X Bit number
IADR
ICCR
I2C Timeout Control Register 15 Address: 000087H Read/write Initial value I2C Timeout Clock Register 7 Address: 000088H Read/write Initial value I2C Timeout Data Register 15 Address: 000089H Read/write Initial value I2C Slave Timeout Register 7 Address: 00008AH Read/write Initial value I2C Master Timeout Register 15 Address: 00008BH Read/write Initial value M7 R/W 0 14 M6 R/W 0 13 M5 R/W 0 12 M4 R/W 0 11 M3 R/W 0 10 M2 R/W 0 9 M1 R/W 0 8 M0 R/W 0 Bit number S6 R/W 0 6 S6 R/W 0 5 S5 R/W 0 4 S4 R/W 0 3 S3 R/W 0 2 S2 R/W 0 1 S1 R/W 0 0 S0 R/W 0 Bit number D7 R/W 0 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Bit number C7 R/W 0 6 C6 R/W 0 5 C5 R/W 0 4 C4 R/W 0 3 C3 R/W 0 2 C2 R/W 0 1 C1 R/W 0 0 C0 R/W 0 Bit number 14 AAC R/W 0 13 12 TOE R/W 0 11 EXT R/W 0 10 TS2 R/W 0 9 TS1 R/W 0 8 TS0 R/W 0 Bit number
ITCR
ITOC
ITOD
ISTO
IMTO
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MB90370 Series
(2) Block diagram of I2C
I 2 C enable ICCR DMBP EN CS4 CS3 CS2 CS1 CS0 IBSRL BB RSC LRB TRX FBT AL IBCRH BER BEIE Interrupt #26 INTE INT SCC MSS ACK GCAA IBCRL LBT IBSRL AAS GCA Slave General call IADR register ITCR IBSRH TDR ITOD IBCRL ITOC ISTO IMTO WUE WUF IBSRH Interrupt #31 TCR MTR STR SDA line Timeout detector Slave address comparator CRC-8 calculator IDAR register End Start Master Enables ACK Enables GC-ACK Bus busy Repeat start Last bit Transmission/ reception Start/stop condition detector Error First byte Arbitration lost detector Clock frequency divider 1 5 6 7 8 Peripheral clock
Clock selector 1
Clock frequency divider 2 4 8 16 32 64 128 256 512 Sync Shift clock generator
Clock selector 2
Shift clock edge
Start/stop condition generator
SCL line
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MB90370 Series
9. MI2C
The Multi-address I2C (Inter IC Bus) interface is a simple structure bidirectional bus consisting of two wires : a serial data line (SDA) and a serial clock line (SCL). Among the devices connected with these two wires, information is transmitted to one another. By recognizing the unique address of each device, it can operate as a transmitting or receiving device in accordance with the function of each device. Among these devices, the master/ slave relation is established. The Multi-address I2C interface can connect two or more devices to the bus provided the upper limit of the bus capacitance does not exceed 400 pF. It is a full-fledged multi-master bus equipped with collision detection and communication adjustment procedures designed to avoid the destruction of data if two or more masters attempt to start data transfer simultaneously. This macro provides 6 addresses to implement the multi-address function. The communication adjustment procedure permits only one master to control the bus when two or more masters attempt to control the bus so that messages are not lost or the contents of messages are not changed. Multimaster means that multiple masters attempt to control the bus simultaneously without losing messages. This Multi-address I2 C interface includes MCU standby mode wake-up function, and a CRC-8 calculator that performs automatic Packet Error Code (PEC) generation and verification. (1) Register configuration of MI2C
Multi-address I2C Bus Control Register (Lower) 7 Address: 0000C0H Read/write Initial value 6 5 4 3 RES R/W 0 2 PECE R/W 0 1 LBT R/W 0 0 WUE R/W 0 Bit number
MBCRL
Multi-address I 2C Bus Control Register (Upper) 15 Address: 0000C1H Read/write Initial value BER R/W 0 14 BEIE R/W 0 13 SCC R/W 0 12 MSS R/W 0 11 ACK R/W 0 10 GCAA R/W 0 9 INTE R/W 0 8 INT R/W 0 Bit number
MBCRH
Multi-address I2C Bus Status Register (Lower) 7 Address: 0000C2H Read/write Initial value BB R 0 6 RSC R 0 5 AL R 0 4 LRB R 0 3 TRX R 0 2 AAS R 0 1 GCA R 0 0 FBT R 0 Bit number
MBSRL
Multi-address I 2C Bus Status Register (Upper) 15 Address: 0000C3H Read/write Initial value 14 13
PMATCH
12 WUF R/W 0
11 TDR R/W 0
10 TCR R/W 0
9 MTR R/W 0
8 STR R/W 0
Bit number
MBSRH
R 0
Multi-address I2C Data Register 7 Address: 0000C4H Read/write Initial value D7 R/W X 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Bit number
MDAR
(Continued) 61
MB90370 Series
(Continued)
Multi-address I2C Alert Register 15 Address: 0000C5H Read/write Initial value 14 13 12 11 ARAE R/W 0 10 ARO R/W 0 9 ARF R/W 0 8 AEN R/W 0 Bit number
MALR
Multi-address I2C Address Register 1/3/5 7 Address ch1 : 0000C6H Address ch3 : 0000C8H Address ch5 : 0000CAH Read/write Initial value A6 R/W X 6 A5 R/W X 5 A4 R/W X 4 A3 R/W X 3 A2 R/W X 2 A1 R/W X 1 A0 R/W X 0 Bit number
MADR1/3/5
Multi-address I2C Address Register 2/4/6 15 Address ch2 : 0000C7H Address ch4 : 0000C9H Address ch6 : 0000CBH Read/write Initial value A6 R/W X 14 A5 R/W X 13 A4 R/W X 12 A3 R/W X 11 A2 R/W X 10 A1 R/W X 9 A0 R/W X 8 Bit number
MADR2/4/6
Multi-address I2C Clock Control Register 7 Address: 0000CCH Read/write Initial value DMBP R/W 0 6 5 EN R/W 0 4 CS4 R/W 0 12 TOE R/W 0 3 CS3 R/W 0 2 CS2 R/W 0 1 CS1 R/W 0 0 CS0 R/W 0 Bit number
MCCR
Multi-address I2C Timeout Control Register 15 Address: 0000CDH Read/write Initial value 14 AAC R/W 0 13 11 EXT R/W 0 10 TS2 R/W 0 9 TS1 R/W 0 8 TS0 R/W 0 Bit number
MTCR
Multi-address I2C Timeout Clock Register 7 Address: 0000CEH Read/write Initial value C7 R/W 0 6 C6 R/W 0 5 C5 R/W 0 4 C4 R/W 0 3 C3 R/W 0 2 C2 R/W 0 1 C1 R/W 0 0 C0 R/W 0 Bit number
MTOC
Multi-address I2C Timeout Data Register 15 Address: 0000CFH Read/write Initial value D7 R/W 0 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Bit number
MTOD
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MB90370 Series
(Continued)
Multi-address I2C Slave Timeout Register 7 Address: 0000D0H Read/write Initial value S6 R/W 0 6 S6 R/W 0 5 S5 R/W 0 4 S4 R/W 0 3 S3 R/W 0 2 S2 R/W 0 1 S1 R/W 0 0 S0 R/W 0 Bit number
MSTO
Multi-address I2C Master Timeout Register 15 Address: 0000D1H Read/write Initial value M7 R/W 0 14 M6 R/W 0 13 M5 R/W 0 12 M4 R/W 0 11 M3 R/W 0 10 M2 R/W 0 9 M1 R/W 0 8 M0 R/W 0 Bit number
MMTO
63
MB90370 Series
(2) Block diagram of MI2C
Multi-address I2 C enable MCCR DMBP EN CS4 CS3 CS2 CS1 CS0 MBSRL BB RSC LRB TRX FBT AL MBCRH BER BEIE INTE INT SCC MSS ACK GCAA MBCRL LBT MBSRL AAS GCA CRC-8 calculator MDAR register Slave General call MADR1~6 registers MTCR MBSRH TDR TCR MTR STR MTOD MALR ARAE ARO ARF AEN MBCRL ALERT line WUE WUF MBSRH Interrupt #33 MMTO MTOC MSTO SDA line Timeout detector End Start Master Enables ACK Enables GC-ACK Interrupt #29 Bus busy Repeat start Last bit Transmission/ reception Start/stop condition detector Error First byte Arbitration lost detector Clock frequency divider 1 5 6 7 8 Peripheral clock
Clock selector 1
Clock frequency divider 2 4 8 16 32 64 128 256 512 Sync Shift clock generator
Clock selector 2
Shift clock edge
Start/stop condition generator
Slave address comparator
SCL line
64
MB90370 Series
10. Bridge circuit
The bridge circuit can switch the I/O path of each port to I2C or Multi-address I2C.
(1) Register configuration of bridge circuit
Bridge Circuit Selection Register 7 Address: 00002CH Read/write Initial value 6 5 BM4 R/W 0 4 BI4 R/W 0 3 BM3 R/W 0 2 BI3 R/W 0 1 BM2 R/W 0 0 BI2 R/W 0 Bit number BRSR
(2) Block diagram of bridge circuit
I2C I/O Multi-address I2C BRSR P91/SDA2 P90/SCL2 BM2 P93/SDA3 P92/SCL3 BM3 P95/SDA4 P94/SCL4 BM4 I2C BI2 P81/SDA1 P80/SCL1
BI3
BI4
65
MB90370 Series
11. Comparator
This comparator circuit monitors voltage of up to three batteries and automatically controls electric discharge. Either parallel discharge or sequential discharge can be selected.
* Parallel discharge control
In parallel discharge control, all batteries are allowed to discharge when power is not being supplied from the AC adapter. * If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled by software.
* Sequential discharge control
In sequential discharge control, the comparator controls discharge in a specified order, while monitoring intermittent interruption of power, voltage level, and mount/dismount of batteries, when power is not being supplied from the AC adapter. * If power is being supplied from the AC adapter, the permission/prohibition of discharge for batteries is controlled by software. * Up to three batteries can be controlled, and the order of discharge can be selected. * * * The affect of intermittent interruption of power is automatically filtered. Mount/dismount of batteries is automatically detected and discharge is controlled. Battery voltage is monitored, and if battery voltage is below the specified voltage, change over to the next battery is automatically done.
66
MB90370 Series
(1) Register configuration of comparator
Comparator Control Register (Lower) 7 Address: 0000D8H Read/write Initial value 6 5 BOF3 R/W 0 4 BOF2 R/W 0 3 2 1 SPM1 R/W 0 0 SPM0 R/W 0 Bit number
BOF1 SPM2 R/W 0 R/W 0
COCRL
Comparator Control Register (Upper) 15 Address: 0000D9H Read/write Initial value SPL3 R/W 0 14 SPL2 R/W 0 13 SPL1 R/W 0 12 B3 R/W 1 11 B2 R/W 1 10 B1 R/W 1 9 DC2 R/W 1 8 DC1 R/W 1 Bit number
COCRH
Comparator Status Register 1 (Lower) 7 Address: 0000DAH Read/write Initial value COR8 R/W 0 6 COR7 R/W 0 5 COR6 R/W 0 4 COR5 R/W 0 3 2 1 COR2 R/W 0 0 COR1 R/W 0 Bit number
COR4 COR3 R/W 0 R/W 0
COSRL1
Comparator Status Register 1 (Upper) 15 Address: 0000DBH Read/write Initial value 14 13 12 11 SW1 R/W 0 10 VAR3 R/W 0 9 VAR2 R/W 0 8 VAR1 R/W 0 Bit number
SWR3 SWR2 R/W 0 R/W 0
COSRH1
Comparator Interrupt Control Register (Lower) 7 Address: 0000DCH Read/write Initial value CEN8 R/W 0 6 CEN7 R/W 0 5 CEN6 R/W 0 4 CEN5 R/W 0 3 CEN4 R/W 0 2 CEN3 R/W 0 1 CEN2 R/W 0 0 CEN1 R/W 0 Bit number
CICRL
(Continued)
67
MB90370 Series
(Continued)
Comparator Interrupt Control Register (Upper) 15 Address: 0000DDH Read/write Initial value 14 13 SEN3 R/W 0 12 SEN2 R/W 0 11 SEN1 R/W 0 10 VEN3 R/W 0 9 VEN2 R/W 0 8 VEN1 R/W 0 Bit number
CICRH
Comparator Status Register 2 (Lower) 7 Address: 0000DEH Read/write Initial value COS8 R X 6 COS7 R X 5 4 3 COS4 R X 2 COS3 R X 1 COS2 R X 0 COS1 R X Bit number
COS6 COS5 R X R X
COSRL2
Comparator Status Register 2 (Upper) 15 Address: 0000DFH Read/write Initial value 14 13 SWS3 R X 12 SWS2 R X 11 10 9 VAL2 R X 8 VAL1 R X Bit number
SWS1 VAL3 R X R X
COSRH2
Comparator Input Enable Register 7 Address: 0000E0H Read/write Initial value 6 5 4 BIE3 R/W 1 3 BIE2 R/W 1 2 BIE1 R/W 1 1 DIE2 R/W 1 0 DIE1 R/W 1 Bit number
CIER
68
MB90370 Series
(2) Block diagram of comparator
Pin PB0/DCIN Pin CVRH2 + Pin CVRL Pin PB1/DCIN2 Pin CVRH1 Pin PB4/VOL2 Pin PB5/VSI2 Pin PC1/AN1/SW2 IN OUT RH (Voltage RL comparator 5) IN OUT RH (Voltage RL comparator 6) + Comparator 2 Pin PB6/VOL3 Pin PB7/VSI3 Pin PC2/AN2/SW3 IN OUT RH (Voltage RL comparator 7) IN OUT RH (Voltage RL comparator 8) + VOL SPL VALID Battery VSI supervisory circuit 3 ALARM SW OFB O13 VOL SPL VALID O12 Comparator 1 IN OUT RH RL (Voltage
Battery selection circuit
SW
Pin PA3/ACO
comparator 2)
SW
Pin PA4/OFB1 Pin PA1/ALR2
Battery VSI supervisory circuit 2 ALARM SW OFB
SW
SW
Pin PA2/ALR3
Comparator 3
Pin PB2/VOL1 Pin PB3/VSI1 Pin PC0/AN0/SW1 Pin XOA Pin X1A Pin VCC Pin RSTX 3
IN OUT RH (Voltage RL comparator 3) IN OUT RH (Voltage RL comparator 4) + -
VOL
SPL VALID O21 O23
Battery VSI supervisory circuit 1 ALARM SW OFB
SW
Pin PA5/OFB2 Pin PA0/ALR1
SW
Comparator 4 Watch prescaler O31 Power-on reset O32 SW Pin PA6/OFB3
8
3 SPL3 SPL2 SPL1 B3 B2 B1 DC2 DC1 3 3 6
COS8 COS7 COS6 COS5 COS4 COS3 COS2 COS1
(COCRH) Comparator control register (upper)
(COSRL2) Comparator status register 2 (lower)
SWR3 SWR2 SWR1 VAR3 VAR2 VAR1
COR8 COR7 COR6 COR5 COR4 COR3 COR2 COR1
(COSRH1) Comparator status register 1 (upper) (CICRH) Comparator interrupt control register (upper) interrupt request #30
SEN3 SEN2 SEN1 VEN3 VEN2 VEN1
(COSRL1) Comparator status register 1 (lower) interrupt request #28 (CICRL) Comparator interrupt control register (lower)
CEN8 CEN7 CEN6 CEN5 CEN4 CEN3 CEN2 CEN1
Decoder
SWS3 SWS2 SWS1 VAL3 VAL2 VAL1
(COSRH2) Comparator status register 2 (upper)
BOF3 BOF2 BOF1 SPM2 SPM1 SPM0
(COCRL) Comparator control register (lower)
Internal data bus
69
MB90370 Series
12. UART (x 3)
The UART (Universal Asychronous Receiver Transmitter) is a serial I/O port for asynchronous (start-stop) communication or clock-synchronous communication. The UART has the following features : * Full-duplex double buffering * Capable of asynchronous (start-stop bit) and CLK-synchronous communications * Support for the multiprocessor mode * Various method of baud rate generation : - External clock input possible - Internal clock (a clock supplied from 16-bit reload timer can be used) - Embedded dedicated baud rate generator Operation Asynchronous Baud rate 76923 / 38461 / 19230 / 9615 / 500K / 250K bps
CLK synchronous 16M / 8M / 4M / 2M / 1M / 500K bps * Error detection functions (parity, framing, overrun) * NRZ (Non Return to Zero) signal format * Interrupt request : - Receive interrupt (receive complete, receive error detection) - Transmit interrupt (transmission complete) - Transmit / receive conforms to extended intelligent I/O service (EI2OS)
70
MB90370 Series
(1) Register configuration of UART
Serial Mode Register 7 Address: ch1 000020H ch2 0000D2H ch3 0000E4H Read/write Initial value Serial Control Register 15 Address: ch1 000021H ch2 0000D3H ch3 0000E5H Read/write Initial value PEN R/W 0 P R/W 0 14 SBL R/W 0 13 CL R/W 0 12 A/D R/W 0 11 REC W 1 10 RXE R/W 0 9 TXE R/W 0 8 Bit number SCR1/2/3 MD1 R/W 0 MD0 R/W 0 6 CS2 R/W 0 5 CS1 R/W 0 4 CS0 R/W 0 3 2 SCKE R/W 0 1 SOE R/W 0 0
Bit number SMR1/2/3
UART Input Data Register / Output Data Register 7 Address: ch1 000022H ch2 0000D4H ch3 0000E6H Read/write Initial value UART Status Register 15 Address: ch1 000023H ch2 0000D5H ch3 0000E7H Read/write Initial value PE R 0 ORE R 0 15 Address: ch1 000025H ch2 0000D7H ch3 0000E9H Read/write Initial value Mode 2 Control Register 7 Address: ch1 000024H ch2 0000D6H ch3 0000E8H Read/write Initial value 6 5 4 SCKL R/W 1 3 M2L2 R/W 0 2 M2L1 R/W 0 1 M2L0 R/W 0 0 Bit number M2CR1/2/3 MD R/W 0 SRST R/W 0 14 14 FRE R 0 13 13 12 11 BDS R/W 0 11 DIV2 R/W 0 10 RIE R/W 0 10 DIV1 R/W 0 9 TIE R/W 0 9 DIV0 R/W 0 8 Bit number CDCR1/2/3 DIV3 R/W 0 8 Bit number SSR1/2/3 RDRF TDRE R 0 12 R 1 D7 R/W X D6 R/W X 6 D5 R/W X 5 D4 R/W X 4 D3 R/W X 3 D2 R/W X 2 D1 R/W X 1 D0 R/W X 0 Bit number SIDR1/2/3 SODR1/2/3
Clock Division Control Register
71
MB90370 Series
(2) Block diagram of UART
From communication prescaler Baud rate generator 16-bit reload timer 1/2/3 P66/UCK1 External clock P70/UI1 Clock selection circuit Transmission clock Reception clock Reception control circuit Start bit detect circuit Reception bit counter Reception parity counter
Reception interrupt #35 (23H)* <#37 (25H)*> <#39 (27H)*> Transmission interrupt #36 (24H)* <#38 (26H)*> <#40 (28H)*>
Transmission control circuit Transmission start circuit Transmission bit counter Transmission parity counter P67/UO1
Reception status judgment circuit
Reception shifter
Transmission shifter
SIDR1/2/3 EI2OS reception error signal (to CPU) F2MC-16LX bus
SODR1/2/3
SMR1/2/3 register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR1/2/3 register
PEN P SBL CL A/D REC RXE TXE
SSR1/2/3 register
PE ORE FRE RDRF TDRE BDS RIE TIE
M2CR1/2/3 register
SCKL M2L2 M2L1 M2L0
*: Interrupt number
Control signal
72
MB90370 Series
13. LCD controller/driver
The LCD (Liquid Crystal Display) controller/driver function displays the contents of a display data memory directly to the LCD panel by segment and common outputs. * Up to nine segment outputs (SEG0 to SEG8) and four common outputs (COM0 to COM3) may be used. * Built-in display RAM. * Three selectable duty ratios (1/2, 1/3, and 1/4). Not all duty ratios are available with all bias settings, however. * Either the main or sub-clock can be selected as the drive clock. * LCD can be driven directly. Table below shows the duty ratios available with each bias setting. Part number MB90370 series 1/3 bias : X: Recommended mode Do not use X Bias 1/2 bias 1/2 duty ratio 1/3 duty ratio X 1/4 duty ratio X
(1) Register configuration of LCD
LCDC Control Register (Upper) 15 Address: 0000EFH Read/write Initial value SS4 R/W 0 14 VS R/W 0 13 CS1 R/W 0 12 CS0 R/W 0 11 SS3 R/W 0 10 SS2 R/W 0 9 SS1 R/W 0 8 SS0 R/W 0 Bit number LCRH
LCDC Control Register (Lower) 7 Address: 0000EEH Read/write Initial value 6 5 4 BK R/W 1 3 MS1 R/W 0 2 MS0 R/W 0 1 FP1 R/W 0 0 FP0 R/W 0 Bit number LCRL
CSS LCEN VSEL R/W 0 R/W 0 R/W 0
73
MB90370 Series
(2) Block diagram of LCD
LCDC supply voltage (V1to V3)
LCDC control register (LCR)
HCLK / 28
4 Prescaler Timing controller 4 V/I converter
Common output driver
Internal bus
Sub-clock (32 kHz)
COM0 COM1 COM2 COM3
9 Display RAM 9 x 4 bit
Controller
Driver
74
Segment output driver
SEG0 SEG1 SEG2 SEG3 SEG4 : SEG5 : SEG6 SEG7 SEG8
MB90370 Series
14. A/D converter
The A/D (Analog to Digital) converter converts the analog voltage input to an analog input pin (input voltage) to a digital value. The converter has the following features : * The minimum conversion time is 6.13 s (for a machine clock of 16 MHz; includes the sampling time). * The minimum sampling time is 3.75 s (for a machine clock of 16 MHz). * The converter uses the RC-type successive approximation conversion method with a sample and hold circuit. * A resolution of 10 bits or 8 bits can be selected. * Up to twelve channels for analog input pins can be selected by a program. * Various conversion mode : - Single conversion mode : Selectively convert one channel. - Scan conversion mode : Continuously convert multiple channels. Maximum of 12 selectable channels. - Continuous conversion mode : Repeatedly convert specified channels. - Stop conversion mode : Convert one channel then halt until the next activation. (Enables synchronization of the conversion start timing.) * At the end of A/D conversion, an interrupt request can be generated and EIOS can be activated. * In the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. * The conversion can be activated by software, 16-bit reload timer 4 (rise edge) and ADTG. (1) Register configuration of A/D converter
Analog Input Enable Register 2 15 Address: 00002BH Read/write Initial value Analog Input Enable Register 1 7 Address: 00002AH Read/write Initial value ADE7 R/W 1 6 ADE6 R/W 1 5 ADE5 R/W 1 4 ADE4 R/W 1 3 ADE3 R/W 1 2 ADE2 R/W 1 1 ADE1 R/W 1 0 ADE0 R/W 1 Bit number 14 13 12 11 10 9 8 Bit number
ADE11 ADE10 ADE9 ADE8 R/W 1 R/W 1 R/W 1 R/W 1
ADER2
ADER1
A/D Control Status Register 1 15 Address: 000031H Read/write Initial value BUSY R/W 0 14 INT R/W 0 13 INTE R/W 0 12 PAUS R/W 0 11 STS1 R/W 0 10 STS0 R/W 0 9 STRT W 0 8 RESV R/W 0 Bit number
ADCS1
A./D Control Status Register 0 7 Address: 000030H Read/write Initial value MD1 R/W 0 6 MD0 R/W 0 5 4 3 2 1 0 Bit number
ADCS0
(Continued) 75
MB90370 Series
(Continued)
A/D Control Register 15 Address: 00002DH Read/write Initial value A/D Data Register (Upper) 15 Address: 00002FH Read/write Initial value A/D Data Register (Lower) 7 Address: 00002EH Read/write Initial value D7 R X 6 D6 R X 5 D5 R X 4 D4 R X 3 D3 R X 2 D2 R X 1 D1 R X 0 D0 R X Bit number S10 R/W 0 14 ST1 W 0 13 ST0 W 0 12 CT1 W 0 11 CT0 W 0 10 9 D9 R X 8 D8 R X Bit number ADCR1 ANS3 R/W 0 14 ANS2 R/W 0 13 ANS1 R/W 0 12 ANS0 R/W 0 11 ANE3 R/W 0 10 ANE2 R/W 0 9 ANE1 R/W 0 8 ANE0 R/W 0 Bit number
ADC0
ADCR0
(2) Block diagram of A/D converter
AVCC AVR AVSS
D/A converter MPX AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Comparator
Sequential compare register
Sample and hold circuit
Data register ADCR0/1
A/D control register A/D control status register 0 A/D control status register 1 ADCS0/1 16-bit reload timer 4 Operation clock P37/ADTG : Machine clock Prescaler
76
MB90370 Series
15. D/A converter
The D/A (Digital to Analog) converter is used to generate an analog output from an 8-bit digital input. By setting the enable bit in the D/A control register (DACR) to 1, it will enable the corresponding D/A output channel. Hence, setting this bit to 0 will disable that channel. If D/A output is disabled, the analog switch inserted to the output of each D/A converter channel in series is turned off. In the D/A converter, the bit is cleared to 0 and the direct-current path is shut off. The above is also true in the stop mode. The output voltage of the D/A converter ranges from 0 V to 255/256 x DVR. To change the output voltage range, adjust the DVR voltage externally. The D/A converter output does not have the internal buffer amplifier. The analog switch (= 100 is inserted to the output in series. To apply load to the output externally, estimate a sufficient stabilization time. Table below lists the theoretical values of output voltage of the D/A converter. Value written to DA07 to DA00 and DA17 to DA10 00H 01H 02H : FDH FEH FFH Theoretical value of output voltage 0/256 DVR (= 0 V) DVR DVR : 253/256 254/256 255/256 DVR DVR DVR
1/256 2/256
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MB90370 Series
(1) Register configuration of D/A converter
D/A converter register 1 Bit Address:00005BH Read/write Initial value
15 R/W X
14 R/W X
13
12
11 DA13 R/W X
10 DA12 R/W X
9
8
DA17 DA16 DA15 DA14 R/W X R/W X
DA11 DA10 DAT1 R/W X R/W X
D/A converter register 0 Bit Address:00005AH Read/write Initial value 7 DA07 R/W X 6 5 4 3 DA03 R/W X 2 DA02 R/W X 1 0
DA06 DA05 DA04 R/W X R/W X R/W X
DA01 DA00 DAT0 R/W X R/W X
D/A control register 1 Bit Address:00005DH Read/write Initial value 15 14 13 12 11 10 9 8 DAE1 DACR1 R/W 0
D/A control register 0 Bit Address:00005CH Read/write Initial value 7 6 5 4 3 2 1 0 DAE0 DACR0 R/W 0
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MB90370 Series
(2) Block diagram of D/A converter
F 2 M2C16LX-BUS
DA DA DA DA DA DA DA DA 17 16 15 14 13 12 11 10
DA DA DA DA DA DA DA DA 07 06 05 04 03 02 01 00
DVR DA17 2R R DA16 2R R DA15 DA05 DA06 DA07
DVR
2R R
2R R
DA11 2R R DA10 2R 2R DAE1
DA01 2R R DA00 2R 2R DAE0
Standby control
Standby control
DA output ch.1
DA output ch.0
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MB90370 Series
16. LPC interface
The LPC (Low Pin Count) interface consists of an LPC bus interface, universal parallel interface (UPI x 4 channels), gate address A20 function and LPC data buffer array. By using the LPC bus interface and UPI, data can be exchanged with an external host CPU synchronously via an external LPC bus. * LPC bus interface The LPC bus interface provides direct access of host CPU to UPI. * It supports I/O read and I/O write cycle only. Other cycle types will be ignored. * It supports LPC clock running at 33 MHz. * Universal parallel interface, UPI x 4 channels The UPI is used to exchange parallel data to serial data in LPC bus with host CPU. * An 8-bit data will be transmitted or received. * A buffer function is available for independent input and output. * The I/O buffer status can be output externally through LPC bus interface. * Gate address A20 function for UPI channel 0 The GA20 (Gate Address A20) is intended to implement the memory management in a PC architecture. This allows the access to the extended memory needed by the operating system. On-chip logic is provided to speed up the generation of GA20. * Data buffer array The data buffer array is consisted of 32 bytes UP data register and 16 bytes DOWN data register to speed up the data transfer between MCU and external host through LPC bus. (1) Register configuration of LPC bus interface register
LPC Control Register 7 Address: 00006EH Read/write Initial value 6 5 4 3 2 LRF R/W 0 1 LRIE R/W 0 0 LPE R/W 0 Bit number LCR
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MB90370 Series
(2) Register configuration of UPI registers
UPI Address Register (Upper) Address: ch1 00005FH ch2 000061H ch3 000063H Read/write Initial value UPI Address Register (Lower) Address: ch1 00005EH ch2 000060H ch3 000062H Read/write Initial value UPI Control Register (Upper) 15 Address: 000065H Read/write Initial value UPI Control Register (Lower) 7 Address: 000064H Read/write Initial value UPI Status Register Address: ch0 000067H ch1 000069H ch2 00006BH ch3 00006DH Read/write Initial value 15 UF4 R/W 0 UF3 R/W 0 14 UF2 R/W 0 13 UF1 R/W 0 12 A2 R 0 11 UF0 R/W 0 10 IBF R 0 9 OBF R 0 8 Bit number UPS0 ~ 3 6 5 4 3 2 1 0 Bit number UPCL 14 UPE3 R/W 0 13 12 11 10 UPE2 R/W 0 9 8 Bit number UPCH 7 6 5 4 3 2 1 0 Bit number UPAL1 ~ 3 UPA07 UPA06 UPA05 UPA04 UPA03 UPA02 UPA01 UPA00 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 15 14 13 12 11 10 9 8 Bit number UPAH1 ~ 3
UPA15 UPA14 UPA13 UPA12 UPA11 UPA10 UPA09 UPA08 R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X
IBFE3 OBEE3 R/W 0 R/W 0
IBFE2 OBEE2 R/W 0 R/W 0
DBAE UPE1 IBFE1 OBEE1 GA20E UPE0 IBFE0 OBEE0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
UPI Data Input Register / Data Output Register Address: ch0 000066H ch1 000068H ch2 00006AH ch3 00006CH Read/write Initial value 7 UPD7 R/W X 6 5 4 3 2 1 0 Bit number UPDI0 ~ 3 / UPDO0 ~ 3
UPD6 UPD5 UPD4 R/W X R/W X R/W X
UPD3 UPD2 UPD1 UPD0 R/W X R/W X R/W X R/W X
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MB90370 Series
(3) Register configuration of LPC data buffer registers
Data Buffer Array Address Register (Upper) 15 Address: 003FF1H Read/write Initial value DA15 R/W X 14 DA14 R/W X 13 DA13 R/W X 12 DA12 R/W X 11 DA11 R/W X 10 DA10 R/W X 9 DA09 R/W X 8 DA08 R/W X Bit number DBAAH
Data Buffer Array Address Register (Lower) 7 6 Address: 003FF0H Read/write Initial value UP Data Register (upper) Address: ch0 003FC1H ch1 003FC3H ~ chF 003FDFH Read/write Initial value UP Data Register (lower) Address: ch0 003FC0H ch1 003FC2H ~ chF 003FDEH Read/write Initial value DOWN Data Register (upper) Address: ch0 003FE1H ch1 003FE3H ~ ch7 003FEFH Read/write Initial value DOWN Data Register (lower) Address: ch0 003FE0H ch1 003FE2H ~ ch7 003FEEH Read/write Initial value 7 DN07 R X DN06 R X 6 15 DN15 R X DN14 R X 14 DN13 R X 7 UP07 R/W X UP06 R/W X 6 15 UP15 R/W X UP14 R/W X 14 DA07 R/W X DA06 R/W X
5 DA05 R/W X
4 DA04 R/W X
3
2
1 DA01 R/W X
0 DA00 R/W X
Bit number DBAAL
DA03 DA02 R/W X R/W X
13 UP12 R/W X
12 UP11 R/W X
11 UP10 R/W X
10 UP09 R/W X
9 UP08 R/W X
8
Bit number UDRH0 ~ F
UP13 R/W X
5 UP04 R/W X
4 UP03 R/W X
3 UP02 R/W X
2 UP01 R/W X
1 UP00 R/W X
0
Bit number UDRL0 ~ F
UP05 R/W X
13 DN12 R X
12 DN11 R X
11 DN10 R X
10 DN09 R X
9 DN08 R X
8
Bit number DNDH0 ~ 7
5 DN04 R X
4
3
2 DN01 R X
1 DN00 R X
0
Bit number DNDL0 ~ 7
DN05 R X
DN03 DN02 R X R X
(Continued) 82
MB90370 Series
(Continued)
Index Register 7 Address: Read/write Initial value Data Port Register Address: Read/write Initial value 7 DP07 R/W X 6 DP06 R/W X 6 5 IX05 R/W 0 5 DP05 R/W X 4 IX04 R/W 0 4 DP04 R/W X 3 IX03 R/W 0 3 2 IX02 R/W 0 2 1 IX01 R/W 0 1 DP01 R/W X 0 IX00 R/W 0 0 DP00 R/W X Bit number DPR Bit number IXR
DP03 DP02 R/W X R/W X
(4) Block diagram of LPC interface
Address comparator
UPE LPC R/W DBAE R/W comp match
Interrupt request #16 Interrupt request #15 Interrupt request #14 Interrupt request #13 Interrupt request #21
UPI address register, UPAH1~3, UPAL1~3 Data buffer array address register, DBAA
UPI0 ~ 3
UPE IBFE OBEE
UPC
F2MC-16LX internal data bus
UPS
UF4 UF3 UF2 UF1 A2 UF0 IBF OBF LCR LRF LRIE LPE LPC internal data bus
OBF0~3
UPDI
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
LA3 LA2 LA1 LA0 EN R/W
UPDO
UPD7 UPD6 UPD5 UPD4 UPD3 UPD2 UPD1 UPD0
State machine
4
LFRAME LRESET LCLK LAD3~LAD0
UPC
GA20E EN
for UPI0 only GA20 output generator
LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
LPC bus interface
GA20 DBAE
UPC
Data buffer array IXR Index register Data port register DPR
UP data register (32 bytes) DOWN data register (16 bytes)
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MB90370 Series
17. Serial IRQ controller
The serial IRQ controller consists of a 6-channel serial IRQ control circuit and an LPC clock monitor / control circuit. By using this serial IRQ controller, host interrupt requests can be transferred serially through a single signal wire (SERIRQ), synchronized with the LPC clock. * 6-channel serial IRQ control circuit * The 6-channel serial IRQ control circuit consists of a serial interrupt control register (SICR), 4 serial interrupt frame number registers (SIFR1 ~ 4), a protocol state machine and a serial interrupt data latch and output control. * For channel 0A, 0B and 1 ~ 3, if SICR : OBE bit (OBF controlled enable bit) = 0, then serial IRQ can be controlled by software setting of SICR : IRR bit. If SICR : OBE bit = 1, then software control is disabled and serial IRQ is controlled by OBF flag (Output buffer full flag) from LPC UPI0 ~ 3. * For channel 4, serial IRQ can be controlled by software setting of SICR : IRR bit. * For channel 0A and 0B, additional enable bit (SICR : EN0A/0B bit) can be used to latch and keep the OBF0 or IRR0A/0B bit status. * The serial interrupt data latch transfers serial IRQs serially according to their frame number. The frame number for channel 0A is fixed to "IRQ1", for channel 0B is fixed to "IRQ12", and the frame number for channel 1 ~ 4 are software programmable (IRQ1 ~ 15, and IRQ21 ~ 31) by setting the SIFR1 ~ 4. * By monitoring the SERIRQ and the LPC clock pin, the protocol state machine can detect the START frame condition. Then it starts counting the DATA frame and transfers its serial IRQs through SERIRQ. Finally it can switch to continuous/quiet mode operation by determine the STOP frame condition. * The serial interrupt output control support both continuous and quiet mode operation. In continuous mode operation, only the host can initiate the serial IRQs transfer; In quiet mode operation, both the host and slave (e.g. the serial IRQ controller) can initiate the serial IRQs transfer. * LPC clock monitor / control circuit * The LPC clock monitor / control circuit consists of a clock-run monitor / control circuit. By monitoring the clock-run pin (CLKRUN), the clock monitor / control circuit can determine whether the host has stopped LPC clock in quiet mode operation or not. If LPC clock is stopped and the controller want to initiate the serial IRQs transfer, then it can request the host to restart the LPC clock by controlling the CLKRUN pin.
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MB90370 Series
(1) Register configuration of serial IRQ controller
Serial Interrupt Control Register (Lower) 7 Address: 000032H Read/write Initial value EN0B R/W 0 6 EN0A R/W 0 5 IRR4 R/W 0 4 IRR3 R/W 0 3 IRR2 R/W 0 2 IRR1 R/W 0 1 0 Bit number
IRR0B IRR0A R/W 0 R/W 0
SICRL
Serial Interrupt Control Register (Upper) 15 Address: 000033H Read/write Initial value 14 13 12 11 OBE2 R/W 0 10 9 8 Bit number
IRQEN RSEN R/W 0 R/W 0
BUSY OBE3 R 0 R/W 0
OBE1 OBE0B OBE0A R/W 0 R/W 0 R/W 0
SICRH
Serial Interrupt Frame Number Register 1 7 Address: 000034H Read/write Initial value 6 5 LV1 R/W 0 4 FR14 R/W 0 3 FR13 R/W 0 2 FR12 R/W 0 1 FR11 R/W 0 0 FR10 R/W 0 Bit number
SIFR1
Serial Interrupt Frame Number Register 2 15 Address: 000035H Read/write Initial value 14 13 LV2 R/W 0 12 FR24 R/W 0 11 FR23 R/W 0 10 FR22 R/W 0 9 FR21 R/W 0 8 FR20 R/W 0 Bit number
SIFR2
Serial Interrupt Frame Number Register 3 7 Address: 000036H Read/write Initial value 6 5 LV3 R/W 0 4 FR34 R/W 0 3 FR33 R/W 0 2 FR32 R/W 0 1 FR31 R/W 0 0 FR30 R/W 0 Bit number
SIFR3
Serial Interrupt Frame Number Register 4 15 Address: 000037H Read/write Initial value 14 13 LV4 R/W 0 12 FR44 R/W 0 11 FR43 R/W 0 10 FR42 R/W 0 9 FR41 R/W 0 8 FR40 R/W 0 Bit number
SIFR4
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MB90370 Series
(2) Block diagram of the serial IRQ controller
Serial IRQ controller
OBF0 OBF1 OBF2 OBF3 OBF0 OBF1 OBF2 OBF3
6-channel serial IRQ control circuit
}
from UPI0~3 in LPC interface
SIRQ
Pin
SERIRQ
LCLK LCLK stop status
Pin
LCLK
LRESET
Pin
LRESET
LCLK restart request
LPC clock monitor / control circuit
LCLK
LRESET
CRUN
Pin
CLKRUN
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MB90370 Series
(3) Block diagram of the 6-channel serial IRQ control circuit
IRQEN
SIRQ enable
Serial interrupt control register (upper)
SERIRQ busy
OBE0A, OBE0B, OBE1~3
OBF0 OBF1 OBF2 OBF3
Register write disable
Serial interrupt control register (lower)
IRR0A, IRR0B, IRR1~3
Software control
Hardware control
F2MC-16LX bus
Serial IRQ control selector for channel 0A, 0B, 1~3
IRR4 channel 1~4
EN0A, EN0B
Latches for channel 0A, 0B
Serial interrupt frame number register
Serial IRQs frame no. for channel 1~4
Serial interrupt data latch and output control
SIRQO LCLK LRESET
Serial IRQ sample cycle
Frame cycle count
Initiate serial IRQ transfer request
Protocol state machine
SIRQI LCLK stop status LCLK restart request
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MB90370 Series
(4) Block diagram of the LPC clock monitor / control circuit
RSEN
IRQEN
CRUNO enable
F2MC-16LX bus
LCLK restart request
LCLK restart request
LCLK stop status CRUNO Clock-run monitor / control CRUNI LCLK LRESET
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MB90370 Series
18. 3-channel PS/2 interface
The 3-channel PS/2 interface consists of 3 individual channels of PS/2 interface that can be operated concurrently. PS/2 interface is a two wires, bidirectional serial bus providing economical way for data exchange between host (keyboard controller) and device (keyboard / mouse etc).
(1) Register configuration of 3-channel PS/2 interface
PS/2 Interface Mode Register 15 Address: 000059H Read/write Initial value PS/2 Interface Data Register (Ch 1) 15 Address: ch1 000057H Read/write Initial value D7 R/W 0 14 D6 R/W 0 13 D5 R/W 0 12 D4 R/W 0 11 D3 R/W 0 10 D2 R/W 0 9 D1 R/W 0 8 D0 R/W 0 Bit number PSDR1 14 13 12 11 10 9 DIV1 R/W 0 8 DIV0 R/W 0 Bit number PSMR
NFS1 NFS0 R/W 0 R/W 0
PS/2 Interface Data Register (Ch 0, Ch 2) 7 Address: ch0 000056H ch2 000058H Read/write Initial value D7 R/W 0 D6 R/W 0 6 D5 R/W 0 5 D4 R/W 0 4 D3 R/W 0 3 D2 R/W 0 2 D1 R/W 0 1 D0 R/W 0 0 Bit number PSDR0/2
PS/2 Interface Status Register 15 Address: ch0 000051H ch1 000053H ch2 000055H Read/write Initial value PS/2 Interface Control Register 7 Address: ch0 000050H ch1 000052H ch2 000054H Read/write Initial value PS2E R/W 0 6 5 FEDE R/W 0 4 IE R/W 0 3 BREQ R/W 0 2 TE R/W 0 1 RE R/W 0 0 Bit number PSCR0/1/2 PE R 0 FED R 0 14
FRE/NAK
13 RAF R 0
12 TS R 0
11 TBC R 0
10 BNR R 0
9 TC R/W 0
8
Bit number PSSR0/1/2
R 0
89
MB90370 Series
(2) Block diagram of 3-channel PS/2 interface
F2MC-16LX bus
PSCKI0
NFS1 NFS0 DIV1 DIV0 2
Noise filter Noise filter
PSCKO0 Channel 0 transmission/reception circuit PSDAO0 Interrupt request 0
PSDAI0
PSMR
PSCKI1 PSDAI1
Noise filter Noise filter
PSCKO1 Channel 1 transmission/reception circuit PSDAO1 Interrupt request 1
PSCKI2 1/4
Noise filter Noise filter
PSCKO2 Channel 2 transmission/reception circuit PSDAO2 Interrupt request 2
Selector
Prescaler circuit 1/8 1/16 1/32
PSDAI2
Sampling clock
90
MB90370 Series
(3) Block diagram of PS/2 interface transmission/reception circuit (1 channel)
F2MC-16LX bus Sampling clock PSDAI PSCKI SYNDA Synchronous circuit SYNCK PSDR
D7 D6 D5 D4 D3 D2 D1 D0
PSDAO
Start of reception
Start of transmission
Reception control circuit Reception completion detector Parity checker Reception start bit detection circuit Reception enable Reception status judgment circuit
Transmission control circuit Acknowledge reception generator
Parity generator
Transmission completion detector
Transmission enable
PE & FRE
Reception Reception complete active
Acknowledge result
Transmission complete
Transfer break request
Transfer complete processing circuit
PSCKO
Transfer status flags clear Falling edge detection Error flags PS/2 interface interrupt #23 (17H)* ch0/1 #24 (18H)* ch2
PS2E
FEDE
IE
BREQ
TE
RE
PE
FED FRE/ RAF NAK
TS
TBC BNR
TC
PSCR
PSSR
F2MC-16LX bus *: Interrupt number
91
MB90370 Series
19. Parity generator
The parity generator is a simple circuit that generates odd / even parity based on the input data. It consists of a parity generator data register (PGDR), an odd / even parity generation logic and a parity generator control status register (PGCSR). An 8-bit data can be loaded into PGDR, then the parity generator will generate odd / even parity based on the input data. Either odd or even parity can be generated by setting the PGCSR. For odd parity generation, if the number of "1"s in the PGDR is even number, then the parity bit in PGCSR will be set to "1", otherwise the parity bit will be set to "0". For even parity generation, if the number of "1"s in the PGDR is even number, then the parity bit in PGCSR will be set to "0", otherwise the parity bit will be set to "1". Table shows some examples of odd / even parity generation. Input data 0000 0000B 0101 0101B 1000 0000B 1010 1011B Parity bit (odd parity) 1 1 0 0 Parity bit (even parity) 0 0 1 1
(1) Register configuration of parity generator
Parity Generator Data Register 7 Address : 000018H Read/write Initial value D7 R/W X 6 D6 R/W X 5 D5 R/W X 4 D4 R/W X 3 D3 R/W X 2 D2 R/W X 1 D1 R/W X 0 D0 R/W X Bit number
PGDR
Parity Generator Control Status Register 15 Address : 000019H Read/write Initial value PRTY R X 14 13 12 11 10 9 8 PSEL R/W 0 Bit number
PGCSR
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MB90370 Series
(2) Block diagram of parity generator
8
2 F MC16LX Internal bus
Parity generator data register 8
Parity generation logic
result
odd / even
2
Parity generator control status register
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MB90370 Series
20. Bit decoder
The bit decoder is a simple one-hot decoder that can be used together with the keyscan inputs. It consists of a bit data register (BDR), a decoder logic and a bit result register (BRR). A 4-bit encoded data can be loaded into BDR, then the decoder logic will decode the data and store the 16-bit resulted data into BRR. Below shows the decoder's logic table. 4-bit encoded data 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 16-bit resulted data 0000 0000 0000 0001B 0000 0000 0000 0010B 0000 0000 0000 0100B 0000 0000 0000 1000B 0000 0000 0001 0000B 0000 0000 0010 0000B 0000 0000 0100 0000B 0000 0000 1000 0000B 0000 0001 0000 0000B 0000 0010 0000 0000B 0000 0100 0000 0000B 0000 1000 0000 0000B 0001 0000 0000 0000B 0010 0000 0000 0000B 0100 0000 0000 0000B 1000 0000 0000 0000B
(1) Register configuration of bit decoder
Bit Data Register
15
14
13
12
11 D3
10 D2 R/W X
9 D1 R/W X
8 D0 R/W X
Bit number
Address : 0000E1H Read/write Initial value -
BDR
R/W X
Bit Result Register (Upper) 15 Address : 0000E3H Read/write Initial value Bit Result Register (Lower) 7 Address : 0000E2H Read/write Initial value R7 R X 6 R6 R X 5 R5 R X 4 R4 R X 3 R3 R X 2 R2 R X 1 R1 R X 0 R0 R X Bit number R15 R X 14 R14 R X 13 R13 R X 12 R12 R X 11 R11 R X 10 R10 R X 9 R9 R X 8 R8 R X Bit number
BRRH
BRRL
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MB90370 Series
(2) Block diagram of bit decoder
4
2 F MC16LX Internal bus
Bit data register 4
Decoder logic
16 16 Bit result register
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MB90370 Series
21. Wake-up interrupt
The wake-up interrupt circuit detects the signals of the "L" levels input to the external interrupt pins and to generate interrupt request to the CPU. These interrupts can wake up the CPU from standby mode. Wake-up interrupt pins: Wake-up interrupt sources: Interrupt control: Interrupt flag: Interrupt request: (1) Register configuration of wake-up interrupt
Wake-up Interrupt Flag Register 15 Address: 0000ADH Read/write Initial value Wake-up Interrupt Control Register 7 Address: 0000ACH Read/write Initial value EN7 R/W 0 14 13 12 11 10 9 8 WIF R/W 0 Bit number EICR Bit number EIFR
8 pins (P00/KSI0 to P07/KSI7). "L" level signal input to a wake-up interrupt pin. Enables or disables to input wake-up interrupt controlled by wake-up interrupt control register (EICR). IRQ flag bit of wake-up interrupt flag register (EIFR). Flag set when there is an IRQ. Interrupt request #20 is generated if any enabled external interrupt pin goes LOW.
6 EN6 R/W 0
5 EN5 R/W 0
4 EN4 R/W 0
3 EN3 R/W 0
2 EN2 R/W 0
1 EN1 R/W 0
0 EN0 R/W 0
(2) Block diagram of wake-up interrupt
7
6
5
4
3
2
1
0
EICR
P07/KS17 P06/KS16 P05/KS15 P04/KS14 P03/KS13 P02/KS12 P01/KS11 P00/KS10
EIFR
Interrupt Request Generator
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MB90370 Series
22. DTP/External interrupts
The DTP (Data Transfer Peripheral)/external interrupt circuit is activated by the signal supplied to a DTP/external interrupt pin. The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent I/O service (EI2OS). Features of DTP/External interrupt : * Total 6 external interrupt channels * Two request levels ("H" and "L") are provided for the intelligent I/O service * Four request levels (rise/fall edge, fall edge, "H" level and "L" level) are provided for external interrupt requests
(1) Register configuration
DTP/Interrupt Source Register 15 Address: 000027H Read/write Initial value ___ ___ ___
14 ___ ___ ___
13 ER5 R/W 0
12 ER4 R/W 0
11 ER3 R/W 0
10 ER2 R/W 0
9 ER1 R/W 0
8 ER0 R/W 0
Bit number EIRR
DTP/Interrupt Enable Register 7 Address: 000026H Read/write Initial value ___ ___ ___ 6 ___ ___ ___ 5 EN5 R/W 0 4 EN4 R/W 0 3 EN3 R/W 0 2 EN2 R/W 0 1 EN1 R/W 0 0 EN0 R/W 0
Bit number ENIR
Request Level Setting Register (Upper) 15 Address: 000029H Read/write Initial value ___ ___ ___ 14 ___ ___ ___ 13 ___ ___ ___ 12 ___ ___ ___ 11 LB5 R/W 0 10 LA5 R/W 0 9 LB4 R/W 0 8 LA4 R/W 0 Bit number ELVRH
Request Level Setting Register (Lower) 7 6 Address: 000028H Read/write Initial value LB3 R/W 0 LA3 R/W 0
5 LB2 R/W 0
4 LA2 R/W 0
3 LB1 R/W 0
2 LA1 R/W 0
1 LB0 R/W 0
0 LA0 R/W 0
Bit number ELVRL
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MB90370 Series
(2) Block diagram of DTP/External interrupts
Request level setting register (ELVR)
LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
2 2 2 2 2 2
Selector
Pin P60/INT0
Selector
Pin P61/INT1
Pin
Selector
Selector
Pin P62/INT2
Internal data bus
P65/INT5
Pin P64/INT4
Selector
Selector
Pin P63/INT3
ER5
ER4
ER3
ER2
ER1
ER0
DTP/interrupt cause register (EIRR)
Interrupt request number #17(11H) #18(12H) #19(13H)
EN5
EN4
EN3
EN2
EN1
EN0
DTP/interrupt enable register (ENIR)
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MB90370 Series
23. Delayed interrupt generation module
The delayed interrupt generation module is used to generate a task switching interrupt. Interrupt requests to the F2MC-16LX CPU can be generated and cleared by software using this module. (1) Register configuration
Delayed Interrupt Generator Module Register 15 Address: 00009FH Read/write Initial value 14 13 12 11 10 9 8 R0 R/W 0 Bit number DIRR
(2) Block diagram
F2MC-16LX bus
Delayed interrupt cause issuance / cancellation decoder
Interrupt cause latch
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MB90370 Series
24. ROM correction function
When an address matches the value set in the address detection register, the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the CPU executes the INT9 instruction. The address match detection function is implemented by processing using the INT9 interrupt routine. The device contains two address detection registers, each provided with a compare enable bit. When the value set in the address detection register matches an address and the interrupt enable bit is "1", the instruction code to be loaded into the CPU is forced to be replaced with the INT9 instruction code. (1) Register configuration
Program Address Detection Control / Status Register 7 6 5 4 Address: 00009EH Read/write Initial value Program Address Detection Register 0 (Upper Byte) 7 Address: 001FF2H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number PADRH0
3 AD1E R/W 0
2 AD1D R/W 0
1 AD0E R/W 0
0 AD0D R/W 0
Bit number PACSR
Program Address Detection Register 0 (Middle Byte) 15 14 13 12 Address: 001FF1H Read/write Initial value R/W X R/W X R/W X R/W X
11
10
9
8
Bit number PADRM0
R/W X
R/W X
R/W X
R/W X
Program Address Detection Register 0 (Lower Byte) 7 Address: 001FF0H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 Bit number PADRL0
(Continued)
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MB90370 Series
(Continued)
Program Address Detection Register 1 (Upper Byte) 15 Address: 001FF5H Read/write Initial value R/W X R/W X R/W X R/W X R/W X R/W X R/W X R/W X 14 13 12 11 10 9 8 Bit number PADRH1
Program Address Detection Register 1 (Middle Byte) 7 6 5 4 Address: 001FF4H Read/write Initial value R/W X R/W X R/W X R/W X
3
2
1
0
Bit number PADRM1
R/W X
R/W X
R/W X
R/W X
Program Address Detection Register 1 (Lower Byte) 15 14 13 12 Address: 001FF3H Read/write Initial value R/W X R/W X R/W X R/W X
11
10
9
8
Bit number PADRL1
R/W X
R/W X
R/W X
R/W X
(2) Block diagram
Address latch Comparator Address detection register 0/1 F2MC-16LX bus
INT9 command
F2MC-16LX CPU
AD0E/AD1E AD0D/AD1D
PACSR
101
MB90370 Series
25. ROM mirroring function selection module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register configuration
ROM Mirror Function Selection Register 15 Address : 0006FH Read/write Initial value 14 13 12 11 10 9 8 M1 W Bit number ROMM
1
(2) Block diagram
ROM mirroring register
F2MC-16LX bus
Address area FF bank 00 bank
ROM
102
MB90370 Series
26. 512K bit flash memory
The 512K bit flash memory is allocated in the FEH to FFH banks on the CPU memory map. Like masked ROM, flash memory is read-accessible and program-accessible to the CPU using the flash memory interface circuit. The flash memory can be programmed/erased by the instruction from the CPU via the flash memory interface circuit. The flash memory can therefore be reprogrammed (updated) while still on the circuit board under integrated CPU control, allowing program code and data to be improved efficiently. Note that sector operations such as "enable sector protect" cannot be used. Features of 512K bit flash memory : * 64K words x 8 bits / 32K words x 16 bits (16K + 8K + 8K + 32K) sector configuration * Automatic program algorithm (same as the Embedded Algorithm* : MBM29F400TA) * Installation of the deletion temporary stop/delete restart function * Write/delete completion detected by the data polling or toggle bit * Write/delete completion detected by the CPU interrupt * Compatibility with the JEDEC standard-type command * Each sector deletion can be executed (Sectors can be freely combined) * Number of write/delete operations 10,000 times guaranteed * : Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. (1) Register configuration
Flash Memory Control Status Register 7 6 Address: 0000AEH Read/write Initial value INTE RDYINT R/W 0 R/W 0
5 WE R/W 0
4 RDY R 1
3
Reserved
2 LPM1 R/W 0
1
Reserved
0 LPM0 R/W 0
Bit number FMCS
W 0
W 0
103
MB90370 Series
(2) Sector configuration of 512K bit flash memory The 512K bit flash memory has the sector configuration illustrated below. The addresses in the illustration are the upper and lower addresses of each sector. When accessed from the CPU, SA0 and SA1 to SA3 are allocated in the FF bank registers, respectively.
Flash memory SA3 (16 Kbytes)
CPU address FFFFFFH FFC000H FFBFFFH FFA000H
*Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFF H 78000H 77FFFH 70000H
SA2 (8 Kbytes)
SA1 (8 Kbytes)
FF9FFF H FF8000H
SA0 (32 Kbytes)
FF7FFFH FF0000H
* : Writer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel writer. Writer addresses are used to program/erase data using a general-purpose writer.
104
MB90370 Series
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(VSS Parameter Symbol VCC Power supply voltage CVCC AVCC A/D converter reference input voltage Comparator reference input voltage LCD power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level maximum output current AVR CVRH1 CVRH2 CVRL V1 ~ V3 VI1 VI2 VO ICLAMP |ICLAMP| IOL1 IOL2 IOLAV1 "L" level average output current IOLAV2 "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current Power consumption Operating temperature 12 mA Value Min. VSS VSS VSS VSS 0.3 0.3 0.3 0.3 Max. VSS VSS VSS VSS 4.0 4.0 4.0 4.0 Unit V V V V VCC VCC AVCC CVCC CVCC CVCC CVCC *1 AVCC *1 AVR, AVR AVSS AVSS CVSS 0.0 V)
Remarks
VSS VSS VSS VSS VSS
0.3 0.3 0.3 0.3 0.3
VSS VSS VSS VSS VSS
4.0 4.0 4.0 6.0 4.0
V V V V V mA mA mA mA mA
CVRH1, CVRH1 CVSS CVRH2, CVRH2 CVSS CVRL, CVRL CVSS
V1 to V3 must not exceed VCC All pins except P40 ~ P45, P80 ~ P82, P90 ~ P95 *2 P40 ~ P45, P80 ~ P82, P90 ~ P95
*2 *4
-2.0
+2.0 20 10 20 4
*4
All pins except PF0 ~ PF7*3 PF0 ~ PF7*3 All pins except PF0 ~ PF7 Average output current = operating current operating efficiency PF0 ~ PF7 Average output current = operating current operating efficiency
IOL IOLAV IOH IOHAV IOH IOHAV PD TA 40
100 50 10 3 100 50 200 85
mA mA mA mA mA mA mW C 105 Average output current = operating current operating efficiency Average output current = operating current operating efficiency
*3
Average output current = operating current operating efficiency
MB90370 Series
Value Min. 55 Max. 150
Parameter Storage temperature
Symbol Tstg
Unit C
Remarks
*1 : Set AVCC, CVCC and VCC at the same voltage. Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when the power is turned on. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. *4 : - Use within recommended operating conditions. - Use at DC voltage (current). - The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. - The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. - Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the Vcc pin, and this may affect other devices. - Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0V), the power supply is provided from the pins, so that incomplete operation may result. - Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to poerate the power-on reset. - Care must be taken not to leave the +B input pin open. - Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. - Sample recommended circuits:
Input/Output Equivalent circuits Protective diode Vcc Limiting resistance +B input (0V to 16V) N-ch P-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 106
MB90370 Series
2. Recommended Operating Conditions
(VSS Parameter Symbol VCC Power supply voltage *2 A/D converter reference input voltage *3 LCD power supply voltage Operating temperature CVCC VCC AVR Value Min. 3.0 *1 3.3 1.8 0 Max. 3.6 3.6 3.6 AVCC Unit V V V V Remarks Normal operation assurance range Retains the RAM state in stop mode Normal operation assurance range V1 ~ V3 pins (The optimum value is dependent on the LCD element in use.) AVSS CVSS = 0.0 V)
V1 ~ V3
VSS
VCC
V
TA
40
85
C
*1 : The operating voltage varies with the operation frequency. *2 : Set AVCC, CVCC and VCC at the same voltage. *3 : Take care so that AVR, CVRH1, CVRH2 and CVRL do not exceed VCC + 0.3 V when power is turned on. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
107
MB90370 Series
3. DC Characteristics
(VCC Parameter Symbol AVCC CVCC 3.0 V to 3.6 V, VSS Condition AVSS Min. CVSS Value Typ. Max. 0.0 V, TA 40 C to 85 C) Unit Remarks Pin name P10 ~ P17 P20 ~ P27 P30 ~ P37 P46 ~ P47 P50 ~ P57 PA0 ~ PA6 PB0 ~ PB7 PC0 ~ PC7 PD0 ~ PD7 PF0 ~ PF7 P00 ~ P07 P60 ~ P67 P70 ~ P77 PE0 ~ PE7 RST P40 ~ P45
VIH
0.7 VCC
VCC 0.3
V
CMOS input pins
"H" level input voltage
VIHS
0.8 VCC
VCC 0.3
V
CMOS hysteresis input pins 5 V tolerant CMOS hysteresis input pins 5 V tolerant CMOS input pin SMbus input pins Mode pins
VIHS5
0.8 VCC
VSS + 5.5
V
VIH5 VIHSM VIHM
P82 P80 ~ P81 P90 ~ P95 MD0 ~ MD2 P10 ~ P17 P20 ~ P27 P30 ~ P37 P46 ~ P47 P50 ~ P57 P82 PA0 ~ PA6 PB0 ~ PB7 PC0 ~ PC7 PD0 ~ PD7 PF0 ~ PF7 P00 ~ P07 P40 ~ P45 P60 ~ P67 P70 ~ P77 PE0 ~ PE7 RST P80 ~ P81 P90 ~ P95 MD0 ~ MD2
0.7 VCC 2.1 VCC 0.3
VSS + 5.5 VSS + 5.5 VCC 0.3
V V V
VIL
VSS
0.3
0.3 VCC
V
CMOS input pins
"L" level input voltage
VILS
VSS
0.3
0.2 VCC
V
CMOS hysteresis input pins SMbus input pins Mode pins
VILSM VILM
VSS VSS
0.3 0.3
0.8 VSS + 0.3
V V
108
MB90370 Series
Parameter Open-drain output pin application voltage Symbol Pin name P40 ~ P45 P80 ~ P82 P90 ~ P95 P46 All port pins except P40 ~ P46 P80 ~ P82 P90 ~ P95 PF0 ~ PF7 PF0 ~ PF7 All port pins except PF0 ~ PF7 PF0 ~ PF7 All input pins P40 ~ P46 P80 ~ P82 P90 ~ P95 Condition Value Typ. Unit Remarks
Min. VSS VSS 0.3 0.3
Max. VSS + 5.5 VCC 0.3
VD5 VD
V V
"H" level output voltage
VOH1
VCC IOH1
3.0 V 4.0 mA
VCC
0.5
V
VOH2 "L" level output voltage Input leakage current (Hi-Z output leakage current) Open-drain output leakage current VOL1 VOL2 IIL
VCC IOH2 IOL1 IOL2 VCC VSS
3.0 V 8.0 mA 4.0 mA 12.0 mA 3.3 V, VI VCC
VCC
0.5 0.4 0.4 5 5
V V V A
ILEAK
5
A
109
MB90370 Series
Parameter Symbol Pin name Condition VCC 3.3 V, Internal operation at 16 MHz VCC 3.3 V, Internal operation at 16 MHz, In sleep mode VCC 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock mode, TA 25 C VCC 3.3 V, External 32 kHz, Internal operation at 8 kHz, In sub-clock sleep mode, TA 25 C VCC 3.3 V, External 32 kHz, Internal operation at 8 kHz, In watch mode, TA 25 C VCC 3.3 V, Internal operation at 16 MHz, In timebase timer mode VCC 3.3 V, In stop mode, TA 25 C All input pins except VCC, AVCC, CVCC, VSS, AVSS, CVSS Between VCC and V3 at VCC = 3.3 V LCD divided resistance RLCD Between V3 and V2 Between V2 and V1 Between V1 and VSS at VCC = 3.3 V 100 Value Typ. 37 30 Unit Remarks
Min.
Max. 45 TBD
mA MB90F372 mA MB90372
ICC
ICCS
15
20
mA
ICCL Power supply current*
23
80
A
VCC
ICCLS
10
50
A
ICCWAT
1.5
30
A
ICCT Power supply current* ICCH VCC
1.3
2
mA
1
20
A
Input capacitance
CIN
10
80
pF
200
400 k
50
100
200
110
MB90370 Series
Parameter COM0 ~ COM3 output impedance SEG0 ~ SEG8 output impedance LCD leakage current Symbol Pin name Condition Value Typ. Unit Remarks
Min.
Max. 5
RVCOM
COM0 ~ COM3 V1 ~ V3 = 3.3 V
k
RVSEG
SEG0 ~ SEG8 V1 ~ V3 COM0 ~ COM3 SEG0 ~ SEG8 P00 ~ P07 P10 ~ P17 P20 ~ P27 P30 ~ P37 RST MD2
5
k
LLCDL
1
A
Pull-up resistance
RUP
25
50
100
k
Pull-down resistance
RDOWN
25
50
100
k
MB90V370, MB90372 only
* : The current value is preliminary value and may be subject to change for enhanced characteristics without previous notice. The power supply current is measured with an external clock.
111
MB90370 Series
4. AC Characteristics
(1) Clock Timings (VCC Parameter AVCC CVCC 3.0 V to 3.6 V, VSS Min. 3 3 32.768 31.25 30.5 5 X0 X0A X0 1.5 8.192 62.5 122.1 666 5 15.2 5 16 333 AVSS Value Typ. Max. 16 32 CVSS 0.0 V, TA Unit 40 C to 85 C) Remarks
Symbol Pin name Condition FCH X0, X1 X0, X1 X0A, X1A X0, X1 X0A, X1A
MHz Crystal oscillator MHz External clock kHz ns s % ns s ns Recommend duty ratio of 30% to 70% Recommend duty ratio of 30% to 70% External clock operation
Clock frequency
FCH FCL tHCYL tLCYL f PWH PWL PWHL PWLL tCR tCF fCP fLCP tCP tLCP
Clock cycle time Frequency fluctuation rate locked*
Input clock pulse width
Input clock rise/fall time Internal operating clock frequency Internal operating clock cycle time
MHz Main clock operation kHz Sub-clock operation ns s Main clock operation Sub-clock operation
*: The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.
f= fo
x 100 (%)
Center frequency
fo
112
MB90370 Series
X0, X1 clock timing
tHCYL 0.8VCC X0 PWH tCF PWL tCR 0.2VCC
X0A, X1A clock timing
tLCYL 0.8VCC X0A PWHL tCF PWLL tCR 0.2VCC
113
MB90370 Series
PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage Power supply voltage VCC (V)
3.6 Operation guarantee range of PLL 3.0
Normal operation guarantee range
1.5 4 Internal operating clock fCP (MHz)
16
Relationship between oscillating frequency and internal operating clock frequency Internal operating clock fCP (MHz)
Multiplied- Multipliedby-3 by-4 Multipliedby-2 Multipliedby-1
16 12 9 8 6 4 3
Not multiplied
3
4
8 Oscillation clock FC (MHz)
16
114
MB90370 Series
The AC ratings are measured for the following measurement reference voltages:
Input signal waveform Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC 0.2 VCC
2.4 V 0.8 V
CMOS input pin
0.7 VCC 0.3 VCC
SMbus input pin
2.1 V 0.8 V
115
MB90370 Series
(2) Reset Input Timing (VCC Parameter Symbol AVCC CVCC 3.0 V to 3.6 V, VSS Min. 16 tCP Reset input time tRSTL RST Oscillation time of oscillator* + 16 tCP AVSS Value Max. CVSS 0.0 V, TA Unit ns 40 C to 85 C) Remarks Normal operation In stop mode and sub-clock mode
Pin name
Condition
ms
* : Oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. In stop mode tRSTL RST 0.2VCC 0.2VCC
90% of the oscillation amplitude X0
Internal operation clock Oscillation time of oscillator 16tCP
Oscillator stabilization time
Internal reset
Instruction execution
116
MB90370 Series
(3) Power-on Reset (VCC Parameter Power supply rise time Power supply cut-off time AVCC CVCC 3.0 V to 3.6 V, VSS Min. AVSS Value Max. 50 1 CVSS 0.0 V, TA Unit ms ms Due to repeated operations 40 C to 85 C) Remarks
Symbol Pin name Condition tR tOFF VCC* VCC*
* : VCC must be kept lower than 0.2 V before power-on. Note: The above values are used for causing a power-on reset. Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn on the power supply using the above values. Note: Make sure that power supply rises within the selected oscillation stabilization time. If the power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.2V 0.2V VCC 0.2V
tOFF
0.2V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommneded to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 mV or fewer per second, however, you can use the PLL clock. VCC It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
1.8V RAM data hold VSS
117
MB90370 Series
(4) UART1 to UART3 (VCC Parameter Serial clock cycle time UCK Valid UI UCK UO delay time UCK valid UI hold time AVCC Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX CVCC 3.0 V to 3.6 V, VSS AVSS CVSS 0.0 V, TA Value Min. 8 tCP CL = 80 pF + 1 TTL for an output pin of internal shift clock mode 80 100 tCP 4 tCP 4 tCP CL = 80 pF + 1 TTL for an output pin of external shift clock mode 150 60 60 80 Max. 40 C to 85 C) Unit Remarks ns ns ns ns ns ns ns ns ns
Pin name UCK1 ~ UCK3 UCK1 ~ UCK3 UO1 ~ UO3 UCK1 ~ UCK3 UI1 ~ UI3 UCK1 ~ UCK3 UI1 ~ UI3 UCK1 ~ UCK3 UCK1 ~ UCK3 UCK1 ~ UCK3 UO1 ~ UO3 UCK1 ~ UCK3 UI1 ~ UI3 UCK1 ~ UCK3 UI1 ~ UI3
Condition
Serial clock "H" pulse width Serial clock "L" pulse width UCK Valid UI UCK Note : UO delay time UCK valid UI hold time
These are AC ratings in the CLK synchronous mode. CL is the load capacitance value connected to pins while testing. tCP is the internal operating clock cycle time.
118
MB90370 Series
Internal shift clock mode tSCYC UCK 2.4V 0.8V tSLOV 0.8V
2.4V UO 0.8V
tIVSH 0.8VCC UI 0.2VCC
tSHIX 0.8VCC 0.2VCC
External shift clock mode tSLSH UCK 0.8VCC 0.2VCC tSLOV 0.2VCC 0.8VCC tSHSL
2.4V UO 0.8V
tIVSH 0.8VCC UI 0.2VCC
tSHIX 0.8VCC 0.2VCC
119
MB90370 Series
(5) Resources Input Timing (VCC Parameter Timer input pulse width
AVCC
CVCC
3.0 V to 3.6 V, VSS Condition
AVSS
CVSS
0.0 V, TA Max.
40 C to 85 C) Unit ns Remarks
Symbol tTIWH tTIWL
Pin name TIN1 ~ TIN4
Value Min. 4 tCP
0.8VCC TIN1 ~ TIN4
0.8VCC 0.2VCC tTIWH tTIWL 0.2VCC
(6) Trigger Input Timing (VCC Parameter Symbol tTRGH tTRGL AVCC CVCC 3.0 V to 3.6 V, VSS Condition Min. 5 tCP 1 AVSS Value Max. CVSS 0.0 V, TA Unit ns s 40 C to 85 C) Remarks Normal operation Stop mode
Pin name ADTG INT0 ~ INT5 KSI0 ~ KSI7
Input pulse width
0.8VCC INT0 ~ INT5 KSI0 ~ KSI7 tTRGH
0.8VCC 0.2VCC tTRGL 0.2VCC
0.7VCC ADTG
0.7VCC 0.3VCC tTRGH tTRGL 0.3VCC
120
MB90370 Series
(7) I2C / MI2C Timing (VCC Parameter Start condition output Stop condition output Start condition detect Stop condition detect Restart condition output Restart condition detect SCL output "L" width SCL output "H" width SDA output delay SDA output setup time after interrupt SCL input "L" pulse SCL input "H" pulse SDA output setup time SDA hold time AVCC CVCC 3.0 V to 3.6 V, VSS Min. tCP (m x n/2 -1) - 20 tCP (m x n/2 + 3) - 20 tCP + 40 tCP + 40 tCP (m x n/2 + 3) - 20 tCP + 40 tCP x m x n/2 - 20 tCP (m x n/2 + 2) - 20 tCP x 3 - 20 tCP x m x n/2 - 20 tCP x 4 - 20 tCP x 3 + 40 tCP + 40 40 0 tCP x m x n/2 + 20 tCP (m x n/2 + 2) + 20 tCP x 3 + 20 tCP (m x n/2 +3) + 20 AVSS Value Max. tCP (m x n/2 -1) + 20 tCP (m x n/2 + 3) + 20 CVSS 0.0 V, TA 40 C to 85 C) Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
*1 *2
Symbol Pin name tSTA tSTO tSTA tSTO tSTASU tSTASU tLOW tHIGH tDO tDOSU tLOW tHIGH tSU tHO SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SDA SCL SCL SDA SDA SCL SCL SDA SDA
Remarks Master mode Master mode
Master mode
Master mode Master mode
Note * tCP is the internal operating clock cycle time. * m is the setting bit of shift clock oscillation defined in the "ICCR register (CS4 ~ CS3)" and "MCCR register (CS4 ~ CS3)". Please refer to the MB90370 series H/W manual for details. * n is the setting bit of shift clock oscillation defined in the "ICCR register (CS2 ~ CS0)" and "MCCR register (CS2 ~ CS0)". Please refer to the MB90370 series H/W manual for details. * tDOSU is shown in the interrupt time is longer than the "L" width of SCL. * SDA and SCL output value is specified on condition that the rise/fall time is "0 ns". *1: At the stop condition or transferring of next byte. *2: After setting register bit IBCRH : SCC at restart.
121
MB90370 Series
Data transmit (master / slave) tDO tDO tSU tHO ACK tSTASU tSTA tLOW tHO 1 9 tDOSU
SDA
SCL
Data receive (master / slave) tSU SDA tHIGH SCL 6 7 tLOW 8 9 tHO tDO ACK tSTO tDO tDOSU
122
MB90370 Series
(8) PS/2 Interface Timing (VCC Parameter PSCK clock cycle time PSCK PSDA Symbol tPCYC tPLOV tPIVSH tPHIX tPHSL tPLSH Pin name PSCK0 ~ 2 PSDA0 ~ 2 PSCK0 ~ 2 Transmission Mode PSDA0 ~ 2 PSCK0 ~ 2 PSDA0 ~ 2 Reception Mode PSCK0 ~ 2 PSDA0 ~ 2 PSCK0 ~ 2 PSDA0 ~ 2 PSCK0 ~ 2 PSDA0 ~ 2 AVCC CVCC 3.0 V to 3.6 V, VSS Min. 4 tCP 2 tCP 1 tCP 1 tCP 2 tCP 2 tCP Value Typ. 0.0 V, TA Max. 40 C to 85 C) Unit Remarks ns ns ns ns ns ns
Condition
Valid PSDA PSCK PSCK valid PSDA hold time PSCK clock "H" pulse width PSCK clock "L" pulse width
Note: tCP is the internal operating clock cycle time.
tPCYC 0.8VCC 0.2VCC
PSCK0 PSCK1 PSCK2
0.8VCC
Transmission Mode PSDA0 PSDA1 PSDA2
tPLOV 2.4V 0.8V
Reception Mode PSDA0 PSDA1 PSDA2
tPIVSH 0.8VCC 0.2VCC
tPHIX
123
MB90370 Series
(9) LPC Timing (VCC Parameter LCLK cycle time LCLK high time LCLK low time AVCC CVCC 3.0 V to 3.6 V, VSS Min. 30 12 12 AVSS CVSS Typ. 0.0 V, TA Max. 40 C to 85 C) Unit ns ns ns Remarks Value
Symbol Pin name Condition tCYCLE tHIGH tLOW
LCLK AC timing tCYCLE tHIGH
0.7VCC 0.3VCC
LCLK tLOW
124
MB90370 Series
LAD, LFRAME, GA20 AC timing
0.4VCC
LCLK
tVAL
OUTPUT Delay tON Tri-state OUTPUT tOFF
0.4VCC
LCLK tS tH
INPUT
125
MB90370 Series
5. A/D Converter Electrical Characteristics
(2.7 V AVR AVSS, VCC Symbol AVCC Pin name CVCC 3.0 V to 3.6 V, VSS Value Min. Typ. Max. 10 3.0 2.5 1.9 AVSS 5.5 LSB AVSS 2.5 LSB AVR 0.5 LSB AVSS CVSS Unit bit LSB LSB LSB For MB90V370 mV For MB90F372/372 mV Actual value is specified as a sum of values specified in ADCR0 : CT1, CT0 and ADCR0 : ST1, ST0. Be sure that the setting value is greater than the min value Actual value is specified in ADCR0 : ST1, ST0 bits. Be sure that the setting value is greater than the min value 0.0 V, TA 40 C to 85 C) Remarks Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage AN0 ~ AN11 AN0 ~ AN11 AVSS 1.5 LSB AVR 3.5 LSB AVSS + 0.5 LSB AVR 1.5 LSB
VOT
VFST
Conversion time
3.1
s
Sampling period Analog port input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Offset between channels IA IAH IR IRH -- AN0 ~ AN11 AN0 ~ AN11 AVR AVCC AVR AN0 ~ AN11
2
s
IAIN VAIN
0.1 AVSS AVSS 2.7 1.4 94
10 AVR AVCC 6.4 5 300 5 4
A V V mA A A A LSB
* *
*: The current when the A/D converter is not operating or the CPU is in stop mode (for VCC = AVCC = AVR = 3.0 V).
126
MB90370 Series
6. A/D Converter Glossary
Resolution : Analog changes that are identifiable with the A/D converter. Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 "11 1111 1111") from actual 0000 0001") with the full-scale transition point ("11 1111 1110" conversion characteristics. Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value. Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Digital output
Actual conversion value
0.5 LSB {1 LSB x (N - 1) + 0.5 LSB}
004 003 002 001 0.5 LSB AVRL Analog input
Actual conversion value Theoretical characteristics
(Measured value)
VNT
AVRH
Total error for digital output N = 1 LSB (Theoretical value)
VNT
{1 LSB [V]
(N 1) 1 LSB
0.5 LSB}
[LSB]
AVR AVss 1024 0.5 LSB [V] 1.5 LSB [V] AVR
VOT (Theoretical value) VFST (Theoretical value)
AVss
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
127
MB90370 Series
(Continued)
Linearity error 3FF 3FE 3FD Digital output
Actual conversion value {1 LSB x (N -1) + VOT}
Differential linearity error
Theoretical characteristics N+1 VFST (Measured value) Actual conversion value
Digital output
N
V(N + 1)T
N-1
004 003 002 001 AVRL
(Measured value) Actual conversion value Theoretical characteristics VOT (Measured value)
VNT
VNT
(Measured value)
N-2
(Measured value) Actual conversion value
AVRH Analog input Linearity error of digital output N Differential linearity error of digital output N 1 LSB VNT V (N
1) T
AVRL Analog input
AVRH
{1 LSB (N 1 LSB VNT
1)
VOT}
[LSB]
1 LSB VFST VOT 1022
1 [LSB] [V]
VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH"
128
MB90370 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 4 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient. Equipment of analog input circuit model Sampling and hold circuit Analog input Comparator R C
R : about 1.9 k C : about 32.3 pF Note: Listed values must be considered as standards.
* Error
The smaller the | AVR - AVSS |, the greater the error would become relatively.
8. D/A Electrical Characteristics
(VCC Parameter Resolution Differential linearity error Non-linearity error Conversion time Analog output impedance Power supply Current IDVR IDVRS AVCC AVCC 0.1 2.0 0.6 2.9 3.8 460 k A A D/A stops AVCC CVCC 3.0 V to 3.6V, VSS Condition AVSS CVSS Value Min. Typ. 8 0.9 1.5 Max. 0.0 V, TA 40 C to 85 C) Unit bit LSB LSB s
*
Symbol Pin name
Remarks
* : With load capacitance is 20 pF.
129
MB90370 Series
9. Comparator Electrical Characteristics
(VCC Parameter AVCC CVCC 3.3 V to 3.6 V, VSS Min. 1.1 CVRL 1.1 AVSS CVSS 0.0 V, TA Max. 2.9 2.9 CVRH1 1 50 10 Unit V V V A A A active inactive 40 C to 85 C) Remarks Value Typ.
Symbol Pin name Condition CVRH2
Reference voltage
CVRH1 CVRL CVRH2 CVRH1 CVRL CVCC DCIN DCIN2 VOL1 ~ 3 VSI1 ~ 3
Reference voltage supply current Comparator supply current
ICR
ICV
Analog input voltage
VIH
CVSS
CVCC
V
10. Serial IRQ Electrical Characteristics
(VCC Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage AVCC CVCC 3.0 V to 3.6 V, VSS Min. 0.7VCC VSS VCC - 0.5 0.4 AVSS CVSS Typ. 0.0 V, TA Max. VCC 0.3VCC 40 C to 85 C) Unit V V V V Remarks Value
Symbol Pin name Condition VIH VIL VOH VOL
11. Flash Memory Program/Erase Characteristics
Value Min. Typ. 1 TA +25 C VCC 3.0 V 4 16 10,000 3,600 Max. 15
Parameter Sector erase time Chip erase time Word (16 bit width) programing time Program/Erase cycle
Condition
Unit s s s V
Remarks Excludes 00H programming prior to erasure Excludes 00H programming prior to erasure Except for the over head time of the system
130
MB90370 Series
EXAMPLE CHARACTERISTICS (MB90F372)
* Power Supply Current
ICC[mA]
50.0
Ta=25[
] Fcin=16[MHz]
ICCS[mA]
1 8.0
Ta=25[
] Fcin= 16[MHz]
1 6.0
40.0
Fcin=12[MHz] Fcin= 10[MHz] Fcin=8[MHz]
1 4.0
Fcin=12[MHz]
1 2.0
30.0
1 0.0
Fcin= 10[MHz] Fcin= 8[MHz]
8.0
20.0
6.0
Fcin= 4[MHz]
1 0.0
4.0
Fcin=4[MHz] Fcin= 2[MHz]
2.0
Fcin=2[MHz]
0.0 2.0 2.5 3.0 3.5
Vcc[V]
4.0
0.0
Vcc[V]
2.0 2.5 3.0 3.5 4.0
ICCH[ A] 2.5
Ta=25[
]
Fc=32.0[kHz]
2.0
1.5
1.0
0.5
0.0 2.5 3.0 3.5 4.0
Vcc[V]
(Continued)
131
MB90370 Series
(Continued)
V CC-VOH1 [V] 2.0
Ta=25[
]
V CC-VOH2[V] 0.7 0.6
Ta=25[
]
1.5 0.5 Vcc=2.5[V] Vcc=2.5[V] 1.0 Vcc=3.0[V] Vcc=3.5[V] Vcc=4.0[V] 0.5 0.3 0.2 0.1 0.0 0 -2 -4 -6 -8 -10 IOH1[mA] 0.0 0 -2 -4 -6 -8 -10 IOH2[mA] 0.4 Vcc=3.0[V] Vcc=3.5[V] Vcc=4.0[V]
VOL1[V] 0.8
Ta=25[
]
VOL2[V] 0.3
Ta=25[
]
0.6
Vcc=2.5[V] Vcc=3.0[V] Vcc=4.0[V] Vcc=3.5[V]
0.2
0.4
Vcc=2.5[V] Vcc=3.0[V] Vcc=3.5[V] Vcc=4.0[V]
0.1 0.2
0.0 0 2 4 6 8 10
IOL1[mA]
0.0 0 2 4 6 8
IOL2[mA] 10
132
MB90370 Series
INSTRUCTIONS (351 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
I S T N Z V C
RMW
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
* Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done the number of cycles suspended as the corrective value to the number of ordinary execution cycles.
133
MB90370 Series
Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
134
MB90370 Series
Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
135
MB90370 Series
Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) Notes: (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
"(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary -- -- +3 Word boundary +2 +3 --
Table 6
Internal memory External data bus (16 bits) External data bus (8 bits) Notes:
When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
136
MB90370 Series
Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b)
Operation byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) byte (A) (dir) (addr16) (Ri) (ear) (eam) (io) imm8 ((A)) ((RLi)+disp8) imm4
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 2 2 2 2+ 3+ (a) 2 3 2 2 2 3 3 10 1 1 2 3 3 4 2 2 2 2 2+ 3+ (a) 2 3 2 2 2 3 2 5 3 10 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2 4 2+ 5+ (a) 2 7 2+ 9+ (a)
- byte (dir) (A) - byte (addr16) (A) - byte (Ri) (A) - byte (ear) (A) - byte (eam) (A) - byte (io) (A) - byte ((RLi) +disp8) (A) - byte (Ri) (ear) - byte (Ri) (eam) - (Ri) byte (ear) - byte (eam) (Ri) - byte (Ri) imm8 - imm8 byte (io) - byte (dir) imm8 - byte (ear) imm8 - byte (eam) imm8 - (b) byte ((A)) (AH) Z 0 (ear) Z 2 (b) byte (A) 0 byte (A) (eam) - 2 (b) byte (Ri) (ear) - byte (Ri) (eam)
byte (A) (dir) (addr16) byte (A) byte (A) (Ri) byte (A) (ear) (eam) byte (A) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8)
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - - - - -
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
137
MB90370 Series
Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A) word (A)
word (A) word (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - ((RWi) +disp8) - ((RLi) +disp8) - (dir) (addr16) (SP) (RWi) (ear) (eam) (io) ((A)) imm16
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP, A MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
- - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - (ear) word (RWi) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - (A) word (dir) word (addr16) (A) word (SP) (A) (A) word (RWi) word (ear) (A) word (eam) (A) word (io) (A) word ((A)) (AH) - - - - - - - - - -
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2 (c) 0 4 2 2 (c) 2 0 0 2 0 0 (d) 0 0 (d)
(ear) word (A) word (A) (eam) word (RWi) (ear) (eam) word (RWi) long (A) long (A) long (A) long (ear) long (eam) (ear) (eam) imm32 (A) (A)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
138
MB90370 Series
Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 (A) +(dir) byte (A) byte (A) (A) +(ear) (A) +(eam) byte (A) (ear) + (A) byte (ear) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z (A) - (ear) byte (A) Z byte (A) (A) - (eam) Z byte (ear) (ear) - (A) - (eam) - (A) byte (eam) - byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z (AH) + (AL) word (A) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) long (A) long (A) long (A) long (A) long (A) (A) + (ear) (A) + (eam) (A) +imm32 (A) - (ear) (A) - (eam) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 2+ 7+ (a) A, eam 4 A, #imm32 5 6 A, ear 2 A, eam 2+ 7+ (a) 4 A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
139
MB90370 Series
Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # 2 2+ 2 2+ 2 2+ 2 2+ 2 2+ 2 2+ ~ 2 5+ (a) 3 5+ (a) 3 5+ (a) 3 5+ (a) 7 9+ (a) 7 9+ (a)
RG
B
Operation (ear) +1 (eam) +1 (ear) -1 (eam) -1 (ear) +1 (eam) +1 (ear) -1 (eam) -1 (ear) +1 (eam) +1 (ear) -1 (eam) -1
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0 2 0 4 0 4 0
byte (ear) 0 2 (b) byte (eam) 0 byte (ear) 2 (b) byte (eam) word (ear) 0 2 (c) word (eam) 0 word (ear) 2 (c) word (eam) long (ear) 0 2 (d) long (eam) 0 long (ear) 2 (d) long (eam)
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) (ear) byte (A) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) word (A) word (A) (ear) (eam) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
140
MB90370 Series
Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Quotient
Operation
byte (AL) Remainder byte (A) Remainder byte (A) Remainder word (A) Remainder word (A) Remainder byte (AH)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
Quotient byte (ear)
- - -
byte (eam)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam)
Quotient
DIVUW A, ear
0 long (A)/word (ear)
Quotient word (ear)
- -
word (ear)
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
Quotient
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
- - - - - -
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 (b) normally. (c) when the result is zero or when an overflow occurs, and 2 (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
141
MB90370 Series
Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) byte (AL) Quotient Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) byte (ear) Remainder *6 word (A)/byte (eam) Quotient byte (A) byte (eam) Remainder 0 long (A)/word (ear) Quotient word (A) word (ear) Remainder *7 long (A)/word (eam) word (A) Quotient Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) byte (A) *byte (ear) byte (A) *byte (eam) word (AH) *word (AL) word (A) *word (ear) word (A) *word (eam) word (A) word (A) word (A) long (A) long (A) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend:Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 6 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
142
MB90370 Series
Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b)
Operation byte (A) (A) and imm8 (A) and (ear) byte (A) byte (A) (A) and (eam) (ear) and (A) byte (ear) (eam) and (A) byte (eam) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) (eam) or (A) byte (eam) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) (ear) xor (A) byte (ear) byte (eam) (eam) xor (A)
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2 (b) byte (eam) not (eam) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) word (A) word (A) word (A) word (A) word (ear) word (eam) (AH) and (A) (A) and imm16 (A) and (ear) (A) and (eam) (ear) and (A) (eam) and (A)
R- R- R- R R R R R R R R R R R R R R R R R R - - - - - - - - - - - - - - - - - -
2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A 2+ 5+ (a) eam, A 2 1 A 2 A, #imm16 3 3 2 A, ear 2+ 4+ (a) A, eam 3 2 ear, A eam, A 2+ 5+ (a) 1 2 3 2 2+ 5+ (a)
word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) word (A) word (A) word (A) word (ear) word (eam) (AH) xor (A) (A) xor imm16 (A) xor (ear) (A) xor (eam) (ear) xor (A) (eam) xor (A)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) not (ear) 0 word (ear) 2 (c) word (eam) not (eam)
R- R- R-
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
143
MB90370 Series
Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) long (A) long (A) long (A) long (A) long (A) (A) and (ear) (A) and (eam) (A) or (ear) (A) or (eam) (A) xor (ear) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A) 0 - (ear) 0 - (eam) 0 - (A) 0 - (ear) 0 - (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
byte (ear) 0 2 (b) byte (eam) 0 word (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
word (ear) 0 2 (c) word (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
144
MB90370 Series
Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
byte (A) byte (A) byte (ear) byte (eam) byte (ear) byte (eam)
byte (A) byte (A) byte (A) word (A)
Operation
Right rotation with carry Left rotation with carry Right rotation with carry Right rotation with carry Left rotation with carry Left rotation with carry
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2 (b) 0 2 0 2 (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Arithmetic right barrel shift (A, R0) Logical right barrel shift (A, R0) Logical left barrel shift (A, R0) Arithmetic right shift (A, 1 bit)
--* --* ---
ASRW A 1 LSRW A/SHRW A 1 LSLW A/SHLW A 1 ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) word (A)
word (A) R0) word (A) word (A)
Logical right shift (A, 1 bit) Logical left shift (A, 1 bit)
Arithmetic right barrel shift (A, Logical right barrel shift (A, R0) Logical left barrel shift (A, R0) Logical right barrel shift (A, R0) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
2 2 2 2 2 2
long (A)
long (A) long (A)
Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
145
MB90370 Series
Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) word (PC) word (PC) word (PC)
word (PC) word (PC)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
(A) addr16 (ear) (eam)
(ear +2) (eam +2)
(ear), (PCB) (eam), (PCB)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2 (c) (c) 2 (c) 2 (c) *2 2 (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 (eam) 0 to 15, word (PC) (PCB) (eam) 16 to 23 word (PC) addr0 to 15, addr16 to 23 (PCB)
4 when branching, 3 when not branching. (b) + 3 (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
146
MB90370 Series
Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4 4
~ * *1
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----** ----** - - - - - - - - - - - - - - - - * * * * * * * *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*10 4+
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
*2 *3 5 *4 5+ *3 3 *5
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2 (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2 (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8 6 6 8 (c) (c) (c) (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----** ----** ----** ----** - - - - - R R R R * S S S S * - - - - * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#local8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 (b) + 2 (c) when an interrupt request occurs, and 6 (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
147
MB90370 Series
Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [28 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) -2n, ((SP)) (rlst) (SP) word (A) ((SP)), (SP) SP) +2 SP) +2 word (AH) ((SP)), (SP) word (PS) ((SP)), (SP) SP) +2 ((SP)), (SP) (SP) +2n (rlst)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - - * - - - - - - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6 (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 byte (CCR) byte (CCR)
AND CCR, #imm8 OR CCR, #imm8 MOV RP, #imm8 MOV ILM, #imm8
(CCR) and imm8 - (CCR) or imm8 - - - - - - - - - Z - - - - - - - -
byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) word (SP) (SP) +ext (imm8) (SP) +imm16
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
byte (A) (brgl) byte (brg2) (A) No operation
Prefix Prefix Prefix Prefix code for accessing AD space code for accessing DT space code for accessing PC space code for accessing SP space
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count (c), or push count (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
148
MB90370 Series
Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) byte (A) byte (A) byte (A) Operation (dir:bp) b (addr16:bp) b (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
(A) 2 (b) bit (dir:bp) b 2 (b) bit (addr16:bp) b (A) 2 (b) bit (io:bp) b (A) 2 (b) bit (dir:bp) b 1 2 (b) bit (addr16:bp) b 1 2 (b) bit (io:bp) b 2 (b) bit (dir:bp) b 0 2 (b) bit (addr16:bp) b 2 (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2 (b) *5 *5 1
0
Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation (A) 8 to 15 byte (A) 0 to 7 (AL) word (AH) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
Note: For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
149
MB90370 Series
Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ Byte transfer @AH-
@AL+, counter = RW0 @AL-, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ Word transfer @AH+ Word transfer @AH- AL, counter = RW0 @AL+, counter = RW0 @AL-, counter = RW0
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 (RW0) for count out, and 7 n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 (RW0) in any other case *3: (b) (RW0) + (b) (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (RW0) *6: (c) (RW0) + (c) (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 6, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
150
MB90370 Series
ORDERING INFORMATION
Part number MB90F372PMT-G MB90372PMT-G-XXX Package 144-pin Plastic LQFP (FPT-144P-M12) Remarks XXX is the ROM release number.
151
MB90370 Series
PACKAGE DIMENSIONS
144-pin plastic LQFP (FPT-144P-M12)
144-pin plastic LQFP
Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight
0.40 mm 16.0 x 16.0 mm Gullwing Plastic mold 1.70 mm MAX 0.88g
(FPT-144P-M12)
18.000.20(.709.008)SQ 16.000.10(.630.004)SQ
108 73
Details of "A" part
109 72
1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.08(.003)
0~8
INDEX 0.45/0.75 (.018/.030)
144 37
0.100.05 (.004.002) (Stand off) 0.25(.010)
"A" LEAD No.
1 36
+0.05
0.40(.016)
0.180.035 .007.001
0.07(.003)
M
0.145 -0.03 .006 -.001
+.002
C
1998 FUJITSU LIMITED F144024S-2C-2
Dimensions mm (inches)
Dimensions in mm (inches)
152
MB90370 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ F0208 FUJITSU LIMITED Printed in Japan
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

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